IMUL (M32)

Operands

• Operand 1 (r): Memory
• Operand 2 (r/w, suppressed): Register (EAX)
• Operand 3 (w, suppressed): Register (EDX)
• Operand 4 (w, suppressed): Flags (AF: undef, CF: w, OF: w, PF: undef, SF: undef, ZF: undef)

Available performance data

• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• Ivy Bridge
• Sandy Bridge
• Westmere
• Nehalem
• Wolfdale
• Conroe
• Tremont
• Goldmont Plus
• Goldmont
• Airmont
• Bonnell
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤9
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤9
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤8
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0156B+1*p06+1*p1+1*p23A (if an indexed addressing mode is used: 1*p06+1*p1+1*p23A)

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 7
  • Latency operand 1 → 2 (address, index register): 7
  • Latency operand 1 → 2 (memory): ≤3
  • Latency operand 1 → 3 (address, base register): 8
  • Latency operand 1 → 3 (address, index register): 8
  • Latency operand 1 → 3 (memory): ≤4
  • Latency operand 1 → 4 (address, base register): 7
  • Latency operand 1 → 4 (address, index register): 7
  • Latency operand 1 → 4 (memory): ≤3
  • Latency operand 2 → 2: 3
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.03
• Number of μops
  • Executed: 2
  • Microcode Sequencer (MS): 0

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤9
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤9
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤8
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00 (if an indexed addressing mode is used: 1.11)
  • Measured (unrolled): 1.00 (if an indexed addressing mode is used: 1.29)
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0156+1*p06+1*p1+1*p23

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤9
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤9
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤8
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00 (if an indexed addressing mode is used: 1.10)
  • Measured (unrolled): 1.00 (if an indexed addressing mode is used: 1.27)
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0156+1*p06+1*p1+1*p23

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤9
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤9
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤8
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00 (if an indexed addressing mode is used: 1.10)
  • Measured (unrolled): 1.00 (if an indexed addressing mode is used: 1.27)
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0156+1*p06+1*p1+1*p23

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤6
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤6
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤5
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00 (if an indexed addressing mode is used: 1.33)
  • Measured (unrolled): 1.00 (if an indexed addressing mode is used: 1.33)
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0156+1*p06+1*p1+1*p23

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤6
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤6
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤6
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 4
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00 (if an indexed addressing mode is used: 1.33)
  • Measured (unrolled): 1.00 (if an indexed addressing mode is used: 1.33)
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0156+1*p06+1*p1+1*p23

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤6
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤6
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤6
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00 (if an indexed addressing mode is used: 1.33)
  • Measured (unrolled): 1.00 (if an indexed addressing mode is used: 1.33)
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0156+1*p06+1*p1+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p1+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p1+1*p23

Coffee Lake

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤6
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤6
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤6
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00 (if an indexed addressing mode is used: 1.33)
  • Measured (unrolled): 1.00 (if an indexed addressing mode is used: 1.33)
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0156+1*p06+1*p1+1*p23

Kaby Lake

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤6
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤6
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤5
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00 (if an indexed addressing mode is used: 1.33)
  • Measured (unrolled): 1.00 (if an indexed addressing mode is used: 1.33)
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0156+1*p06+1*p1+1*p23

Skylake

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤6
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤6
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤6
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00 (if an indexed addressing mode is used: 1.33)
  • Measured (unrolled): 1.00 (if an indexed addressing mode is used: 1.33)
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0156+1*p06+1*p1+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p1+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p1+1*p23

Broadwell

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤8
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤8
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.02 (if an indexed addressing mode is used: 1.33)
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0156+1*p06+1*p1+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p1+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p1+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p1+1*p23

Haswell

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤8
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤7
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.02 (if an indexed addressing mode is used: 1.33)
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0156+1*p06+1*p1+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p1+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p1+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p1+1*p23

Ivy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤8
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤7
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.13 (if an indexed addressing mode is used: 1.33)
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+1*p05+1*p1+1*p23

Sandy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 9
  • Latency operand 1 → 2 (address, index register): 9
  • Latency operand 1 → 2 (memory): ≤8
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤7
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.13 (if an indexed addressing mode is used: 1.33)
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+1*p05+1*p1+1*p23

Westmere

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 8
  • Latency operand 1 → 2 (address, index register): 8
  • Latency operand 1 → 2 (memory): ≤8
  • Latency operand 1 → 3 (address, base register): 8
  • Latency operand 1 → 3 (address, index register): 8
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 7
  • Latency operand 1 → 4 (memory): ≤9
  • Latency operand 2 → 2: 5
  • Latency operand 2 → 3: 5
  • Latency operand 2 → 4: 5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder
• Port usage: 1*p015+1*p05+1*p1+1*p2
• IACA 2.1
• Latency: 12
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 8.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p0+1*p1+1*p2
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 8.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p0+1*p1+1*p2

Nehalem

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 8
  • Latency operand 1 → 2 (address, index register): 8
  • Latency operand 1 → 2 (memory): ≤8
  • Latency operand 1 → 3 (address, base register): 8
  • Latency operand 1 → 3 (address, index register): 8
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 1 → 4 (address, base register): 8
  • Latency operand 1 → 4 (address, index register): 7
  • Latency operand 1 → 4 (memory): ≤9
  • Latency operand 2 → 2: 5
  • Latency operand 2 → 3: 5
  • Latency operand 2 → 4: 5
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder
• Port usage: 1*p015+1*p05+1*p1+1*p2
• IACA 2.1
• Latency: 12
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 8.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p0+1*p1+1*p2
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 8.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p0+1*p1+1*p2

Wolfdale

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 8
  • Latency operand 1 → 2 (address, index register): 8
  • Latency operand 1 → 2 (memory): ≤8
  • Latency operand 1 → 3 (address, base register): 8
  • Latency operand 1 → 3 (address, index register): 8
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 1 → 4 (address, base register): 7
  • Latency operand 1 → 4 (address, index register): 7
  • Latency operand 1 → 4 (memory): ≤8
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 4
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.52
  • Measured (unrolled): 1.48
• Number of μops
  • Executed: 4
• Port usage: 1*p015+1*p05+1*p1+1*p2

Conroe

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 8
  • Latency operand 1 → 2 (address, index register): 8
  • Latency operand 1 → 2 (memory): ≤8
  • Latency operand 1 → 3 (address, base register): 8
  • Latency operand 1 → 3 (address, index register): 8
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 1 → 4 (address, base register): 7
  • Latency operand 1 → 4 (address, index register): 7
  • Latency operand 1 → 4 (memory): ≤8
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 4
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.52
  • Measured (unrolled): 1.50
• Number of μops
  • Executed: 4
• Port usage: 1*p015+1*p05+1*p1+1*p2

Tremont

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 6
  • Latency operand 1 → 2 (address, index register): 6
  • Latency operand 1 → 2 (memory): ≤7
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 7
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 1 → 4 (address, base register): 6
  • Latency operand 1 → 4 (address, index register): 6
  • Latency operand 1 → 4 (memory): ≤7
  • Latency operand 2 → 2: 3
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 2
  • Microcode Sequencer (MS): 0

Goldmont Plus

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 6
  • Latency operand 1 → 2 (address, index register): 6
  • Latency operand 1 → 2 (memory): ≤7
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 7
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 1 → 4 (address, base register): 6
  • Latency operand 1 → 4 (address, index register): 6
  • Latency operand 1 → 4 (memory): ≤7
  • Latency operand 2 → 2: 3
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 2
  • Microcode Sequencer (MS): 0

Goldmont

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 6
  • Latency operand 1 → 2 (address, index register): 6
  • Latency operand 1 → 2 (memory): ≤8
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 7
  • Latency operand 1 → 3 (memory): ≤9
  • Latency operand 1 → 4 (address, base register): 6
  • Latency operand 1 → 4 (address, index register): 6
  • Latency operand 1 → 4 (memory): ≤7
  • Latency operand 2 → 2: 3
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Measured (loop): 2.02
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 2
  • Microcode Sequencer (MS): 0

Airmont

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 7
  • Latency operand 1 → 2 (address, index register): 7
  • Latency operand 1 → 2 (memory): ≤9
  • Latency operand 1 → 3 (address, base register): 8
  • Latency operand 1 → 3 (address, index register): 8
  • Latency operand 1 → 3 (memory): ≤9
  • Latency operand 1 → 4 (address, base register): 6
  • Latency operand 1 → 4 (address, index register): 6
  • Latency operand 1 → 4 (memory): ≤7
  • Latency operand 2 → 2: 4
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 4
• Throughput
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 4
  • Microcode Sequencer (MS): 4
  • Requires the complex decoder

Bonnell

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 10
  • Latency operand 1 → 2 (address, index register): 10
  • Latency operand 1 → 2 (memory): ≤7
  • Latency operand 1 → 3 (address, base register): 10
  • Latency operand 1 → 3 (address, index register): 10
  • Latency operand 1 → 3 (memory): ≤7
  • Latency operand 1 → 4 (address, base register): 10
  • Latency operand 1 → 4 (address, index register): 10
  • Latency operand 1 → 4 (memory): ≤7
  • Latency operand 2 → 2: 7
  • Latency operand 2 → 3: 7
  • Latency operand 2 → 4: 7
• Throughput
  • Measured (loop): 7.02
  • Measured (unrolled): 7.00
• Number of μops
  • Executed: 4
  • Microcode Sequencer (MS): 4
  • Requires the complex decoder

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 7
  • Latency operand 1 → 2 (address, index register): 7
  • Latency operand 1 → 2 (memory): ≤11
  • Latency operand 1 → 3 (address, base register): 8
  • Latency operand 1 → 3 (address, index register): 8
  • Latency operand 1 → 3 (memory): ≤10
  • Latency operand 1 → 4 (address, base register): 7
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤10
  • Latency operand 2 → 2: 3
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Measured (loop): 1.00 (if an indexed addressing mode is used: 2.00)
  • Measured (unrolled): 1.00 (if an indexed addressing mode is used: 2.00)
• Number of μops
  • Executed: 2 (if an indexed addressing mode is used: 3)

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 7
  • Latency operand 1 → 2 (address, index register): 7
  • Latency operand 1 → 2 (memory): ≤12
  • Latency operand 1 → 3 (address, base register): 8
  • Latency operand 1 → 3 (address, index register): 8
  • Latency operand 1 → 3 (memory): ≤11
  • Latency operand 1 → 4 (address, base register): 7
  • Latency operand 1 → 4 (address, index register): 8
  • Latency operand 1 → 4 (memory): ≤10
  • Latency operand 2 → 2: 3
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Measured (loop): 1.00 (if an indexed addressing mode is used: 2.00)
  • Measured (unrolled): 1.00 (if an indexed addressing mode is used: 2.00)
• Number of μops
  • Executed: 2 (if an indexed addressing mode is used: 3)

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 7
  • Latency operand 1 → 2 (address, index register): 7
  • Latency operand 1 → 2 (memory): ≤3
  • Latency operand 1 → 3 (address, base register): 8
  • Latency operand 1 → 3 (address, index register): 8
  • Latency operand 1 → 3 (memory): ≤4
  • Latency operand 1 → 4 (address, base register): 7
  • Latency operand 1 → 4 (address, index register): 7
  • Latency operand 1 → 4 (memory): ≤4
  • Latency operand 2 → 2: 3
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 4
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2

AMD Zen+

• Measurements
• Latencies
  • Latency operand 1 → 2 (address, base register): 7
  • Latency operand 1 → 2 (address, index register): 7
  • Latency operand 1 → 2 (memory): ≤9
  • Latency operand 1 → 3 (address, base register): 8
  • Latency operand 1 → 3 (address, index register): 8
  • Latency operand 1 → 3 (memory): ≤10
  • Latency operand 1 → 4 (address, base register): 7
  • Latency operand 1 → 4 (address, index register): 7
  • Latency operand 1 → 4 (memory): ≤9
  • Latency operand 2 → 2: 3
  • Latency operand 2 → 3: 4
  • Latency operand 2 → 4: 3
• Throughput
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 2