IMUL (M32)

With unroll_count=500 and no inner loop

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 5.81
- Reference cycles: 5.36
- UOPS_RETIRED.ANY: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.17
- UOPS_PORT_1: 1.08
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 5.73
- Reference cycles: 5.29
- UOPS_RETIRED.ANY: 4.2
- RETIRE_SLOTS: 3.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.17
- UOPS_PORT_1: 1.12
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 1.0

With loop_count=100 and unroll_count=100

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 5.79
- Reference cycles: 5.35
- UOPS_RETIRED.ANY: 4.02
- RETIRE_SLOTS: 3.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.15
- UOPS_PORT_1: 1.11
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 1.0

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.83
- UOPS_RETIRED.ANY: 5.0
- RETIRE_SLOTS: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.22
- UOPS_PORT_1: 1.45
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 2.1
- Reference cycles: 1.94
- UOPS_RETIRED.ANY: 5.2
- RETIRE_SLOTS: 4.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.28
- UOPS_PORT_1: 1.45
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 1.0

With loop_count=100 and unroll_count=100

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 2.01
- Reference cycles: 1.86
- UOPS_RETIRED.ANY: 5.02
- RETIRE_SLOTS: 4.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.15
- UOPS_PORT_1: 1.49
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 2.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 1.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 23.4
- Reference cycles: 21.6
- UOPS_RETIRED.ANY: 16.0
- RETIRE_SLOTS: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.7
- UOPS_PORT_1: 4.3
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 23.01
- Reference cycles: 21.23
- UOPS_RETIRED.ANY: 17.0
- RETIRE_SLOTS: 13.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.86
- UOPS_PORT_1: 4.36
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 0.05

With loop_count=100 and unroll_count=20

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 23.16
- Reference cycles: 21.38
- UOPS_RETIRED.ANY: 16.1
- RETIRE_SLOTS: 12.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.64
- UOPS_PORT_1: 4.4
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 4.01

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 7.34
- UOPS_RETIRED.ANY: 20.0
- RETIRE_SLOTS: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.85
- UOPS_PORT_1: 5.8
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 8.51
- Reference cycles: 7.85
- UOPS_RETIRED.ANY: 21.0
- RETIRE_SLOTS: 17.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.03
- UOPS_PORT_1: 6.13
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 4.0

With loop_count=100 and unroll_count=20

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 8.1
- Core cycles: 8.06
- Reference cycles: 7.43
- UOPS_RETIRED.ANY: 20.1
- RETIRE_SLOTS: 16.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.63
- UOPS_PORT_1: 5.99
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 4.0

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 46.8
- Reference cycles: 43.2
- UOPS_RETIRED.ANY: 32.0
- RETIRE_SLOTS: 24.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.4
- UOPS_PORT_1: 8.6
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 46.01
- Reference cycles: 42.47
- UOPS_RETIRED.ANY: 34.0
- RETIRE_SLOTS: 26.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.72
- UOPS_PORT_1: 8.72
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 0.1

With loop_count=100 and unroll_count=10

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 46.32
- Reference cycles: 42.75
- UOPS_RETIRED.ANY: 32.2
- RETIRE_SLOTS: 24.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.29
- UOPS_PORT_1: 8.8
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 8.01

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 15.99
- Reference cycles: 14.72
- UOPS_RETIRED.ANY: 40.0
- RETIRE_SLOTS: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.7
- UOPS_PORT_1: 11.6
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 17.01
- Reference cycles: 15.7
- UOPS_RETIRED.ANY: 42.0
- RETIRE_SLOTS: 34.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 10.05
- UOPS_PORT_1: 12.27
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 8.01

With loop_count=100 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.11
- Reference cycles: 14.87
- UOPS_RETIRED.ANY: 40.2
- RETIRE_SLOTS: 32.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.27
- UOPS_PORT_1: 11.99
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 8.01

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  1f:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  23:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  27:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  2b:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  2f:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  33:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  37:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  3b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 93.6
- Reference cycles: 86.4
- UOPS_RETIRED.ANY: 64.0
- RETIRE_SLOTS: 48.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 18.8
- UOPS_PORT_1: 17.2
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 16.01

With loop_count=1000 and unroll_count=1

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  1f:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  23:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  27:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  2b:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  2f:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  33:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  37:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  3b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 91.34
- Reference cycles: 84.31
- UOPS_RETIRED.ANY: 66.0
- RETIRE_SLOTS: 50.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 19.83
- UOPS_PORT_1: 17.66
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 16.01

With loop_count=100 and unroll_count=10

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  1f:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  23:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  27:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  2b:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  2f:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  33:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  37:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  3b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 92.27
- Reference cycles: 85.16
- UOPS_RETIRED.ANY: 64.2
- RETIRE_SLOTS: 48.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 18.13
- UOPS_PORT_1: 17.69
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 16.01

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  37:	48 31 c0             	xor    rax,rax
  3a:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  3e:	48 31 c0             	xor    rax,rax
  41:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  45:	48 31 c0             	xor    rax,rax
  48:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  4c:	48 31 c0             	xor    rax,rax
  4f:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  53:	48 31 c0             	xor    rax,rax
  56:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  5a:	48 31 c0             	xor    rax,rax
  5d:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  61:	48 31 c0             	xor    rax,rax
  64:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  68:	48 31 c0             	xor    rax,rax
  6b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 32.0
- Core cycles: 31.99
- Reference cycles: 29.44
- UOPS_RETIRED.ANY: 80.0
- RETIRE_SLOTS: 64.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 19.36
- UOPS_PORT_1: 23.27
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  37:	48 31 c0             	xor    rax,rax
  3a:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  3e:	48 31 c0             	xor    rax,rax
  41:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  45:	48 31 c0             	xor    rax,rax
  48:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  4c:	48 31 c0             	xor    rax,rax
  4f:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  53:	48 31 c0             	xor    rax,rax
  56:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  5a:	48 31 c0             	xor    rax,rax
  5d:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  61:	48 31 c0             	xor    rax,rax
  64:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  68:	48 31 c0             	xor    rax,rax
  6b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 34.0
- Core cycles: 33.02
- Reference cycles: 30.47
- UOPS_RETIRED.ANY: 82.0
- RETIRE_SLOTS: 66.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 20.0
- UOPS_PORT_1: 23.86
- UOPS_PORT_2: 16.01
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 16.01

With loop_count=100 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  37:	48 31 c0             	xor    rax,rax
  3a:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  3e:	48 31 c0             	xor    rax,rax
  41:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  45:	48 31 c0             	xor    rax,rax
  48:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  4c:	48 31 c0             	xor    rax,rax
  4f:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  53:	48 31 c0             	xor    rax,rax
  56:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  5a:	48 31 c0             	xor    rax,rax
  5d:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  61:	48 31 c0             	xor    rax,rax
  64:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  68:	48 31 c0             	xor    rax,rax
  6b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 32.2
- Core cycles: 32.12
- Reference cycles: 29.64
- UOPS_RETIRED.ANY: 80.2
- RETIRE_SLOTS: 64.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 18.91
- UOPS_PORT_1: 23.79
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 16.01

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 5.0
- Reference cycles: 4.62
- UOPS_RETIRED.ANY: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.93
- UOPS_PORT_1: 0.99
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.95
- Reference cycles: 4.57
- UOPS_RETIRED.ANY: 4.2
- RETIRE_SLOTS: 4.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.16
- UOPS_PORT_1: 1.05
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 1.0

With loop_count=100 and unroll_count=100

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 5.0
- Reference cycles: 4.61
- UOPS_RETIRED.ANY: 4.02
- RETIRE_SLOTS: 4.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.16
- UOPS_PORT_1: 1.0
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 1.0

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 2.0
- Reference cycles: 1.85
- UOPS_RETIRED.ANY: 5.0
- RETIRE_SLOTS: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.2
- UOPS_PORT_1: 1.46
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 2.1
- Reference cycles: 2.0
- UOPS_RETIRED.ANY: 5.2
- RETIRE_SLOTS: 5.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.31
- UOPS_PORT_1: 1.5
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 1.0

With loop_count=100 and unroll_count=100

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 2.01
- Reference cycles: 1.86
- UOPS_RETIRED.ANY: 5.02
- RETIRE_SLOTS: 5.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.17
- UOPS_PORT_1: 1.48
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 1.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 20.0
- Reference cycles: 18.46
- UOPS_RETIRED.ANY: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 3.7
- UOPS_PORT_1: 4.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 19.75
- Reference cycles: 18.23
- UOPS_RETIRED.ANY: 17.0
- RETIRE_SLOTS: 17.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.37
- UOPS_PORT_1: 4.25
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 0.05

With loop_count=100 and unroll_count=20

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 19.98
- Reference cycles: 18.43
- UOPS_RETIRED.ANY: 16.1
- RETIRE_SLOTS: 16.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.63
- UOPS_PORT_1: 4.02
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 4.01

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.01
- Reference cycles: 7.34
- UOPS_RETIRED.ANY: 20.0
- RETIRE_SLOTS: 20.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.81
- UOPS_PORT_1: 5.83
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 8.51
- Reference cycles: 7.85
- UOPS_RETIRED.ANY: 21.0
- RETIRE_SLOTS: 21.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 5.22
- UOPS_PORT_1: 6.06
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 4.0

With loop_count=100 and unroll_count=20

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.1
- Core cycles: 8.06
- Reference cycles: 7.44
- UOPS_RETIRED.ANY: 20.1
- RETIRE_SLOTS: 20.1
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.67
- UOPS_PORT_1: 5.93
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 4.0

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 39.99
- Reference cycles: 36.88
- UOPS_RETIRED.ANY: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 7.39
- UOPS_PORT_1: 7.99
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 39.5
- Reference cycles: 36.46
- UOPS_RETIRED.ANY: 34.0
- RETIRE_SLOTS: 34.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.75
- UOPS_PORT_1: 8.5
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 0.1

With loop_count=100 and unroll_count=10

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 39.95
- Reference cycles: 36.87
- UOPS_RETIRED.ANY: 32.2
- RETIRE_SLOTS: 32.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.26
- UOPS_PORT_1: 8.05
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 8.01

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.01
- Reference cycles: 14.68
- UOPS_RETIRED.ANY: 40.0
- RETIRE_SLOTS: 40.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.61
- UOPS_PORT_1: 11.66
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 17.02
- Reference cycles: 15.71
- UOPS_RETIRED.ANY: 42.0
- RETIRE_SLOTS: 42.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 10.44
- UOPS_PORT_1: 12.13
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 8.01

With loop_count=100 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.11
- Reference cycles: 14.87
- UOPS_RETIRED.ANY: 40.2
- RETIRE_SLOTS: 40.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.34
- UOPS_PORT_1: 11.86
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 8.01

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  27:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  2c:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  31:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  36:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  3b:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  40:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  45:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  4a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 79.99
- Reference cycles: 73.76
- UOPS_RETIRED.ANY: 64.0
- RETIRE_SLOTS: 64.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 14.77
- UOPS_PORT_1: 15.99
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  27:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  2c:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  31:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  36:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  3b:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  40:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  45:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  4a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 79.5
- Reference cycles: 73.38
- UOPS_RETIRED.ANY: 66.0
- RETIRE_SLOTS: 66.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 18.61
- UOPS_PORT_1: 16.5
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 16.01

With loop_count=100 and unroll_count=10

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  27:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  2c:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  31:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  36:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  3b:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  40:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  45:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  4a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 79.92
- Reference cycles: 73.77
- UOPS_RETIRED.ANY: 64.2
- RETIRE_SLOTS: 64.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 18.54
- UOPS_PORT_1: 16.08
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 16.01

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  3f:	48 31 c0             	xor    rax,rax
  42:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  47:	48 31 c0             	xor    rax,rax
  4a:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  4f:	48 31 c0             	xor    rax,rax
  52:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  57:	48 31 c0             	xor    rax,rax
  5a:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  5f:	48 31 c0             	xor    rax,rax
  62:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  67:	48 31 c0             	xor    rax,rax
  6a:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  6f:	48 31 c0             	xor    rax,rax
  72:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  77:	48 31 c0             	xor    rax,rax
  7a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 32.0
- Core cycles: 32.11
- Reference cycles: 29.64
- UOPS_RETIRED.ANY: 80.0
- RETIRE_SLOTS: 80.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 19.3
- UOPS_PORT_1: 23.3
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 16.01

With loop_count=1000 and unroll_count=1

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  3f:	48 31 c0             	xor    rax,rax
  42:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  47:	48 31 c0             	xor    rax,rax
  4a:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  4f:	48 31 c0             	xor    rax,rax
  52:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  57:	48 31 c0             	xor    rax,rax
  5a:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  5f:	48 31 c0             	xor    rax,rax
  62:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  67:	48 31 c0             	xor    rax,rax
  6a:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  6f:	48 31 c0             	xor    rax,rax
  72:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  77:	48 31 c0             	xor    rax,rax
  7a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 34.0
- Core cycles: 33.01
- Reference cycles: 30.46
- UOPS_RETIRED.ANY: 82.0
- RETIRE_SLOTS: 82.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 20.24
- UOPS_PORT_1: 24.0
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 16.01

With loop_count=100 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  3f:	48 31 c0             	xor    rax,rax
  42:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  47:	48 31 c0             	xor    rax,rax
  4a:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  4f:	48 31 c0             	xor    rax,rax
  52:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  57:	48 31 c0             	xor    rax,rax
  5a:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  5f:	48 31 c0             	xor    rax,rax
  62:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  67:	48 31 c0             	xor    rax,rax
  6a:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  6f:	48 31 c0             	xor    rax,rax
  72:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  77:	48 31 c0             	xor    rax,rax
  7a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 32.2
- Core cycles: 32.11
- Reference cycles: 29.64
- UOPS_RETIRED.ANY: 80.2
- RETIRE_SLOTS: 80.2
- UOPS_MS: 0.0
- UOPS_PORT_0: 18.93
- UOPS_PORT_1: 23.54
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- INST_DECODED.DEC0: 16.01

IMUL (M32) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10