IMUL (M32) - Port Usage

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
   7:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
   e:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  15:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  1c:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  23:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  2a:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  31:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  38:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  3f:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  46:	41 f7 2e             	imul   DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.09
- Reference cycles: 6.57
- UOPS_PORT_1: 11.0

⇨ One μop that can only use port '1'

With blocking instructions for port '23':

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	41 f7 2e             	imul   DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.68
- Reference cycles: 4.71
- UOPS_PORT_23: 17.0

⇨ One μop that can only use port '23'

With blocking instructions for ports {'0', '5'}:

Code:

   0:	0f 6f c1             	movq   mm0,mm1
   3:	0f 6f d1             	movq   mm2,mm1
   6:	0f 6f d9             	movq   mm3,mm1
   9:	0f 6f e1             	movq   mm4,mm1
   c:	0f 6f e9             	movq   mm5,mm1
   f:	0f 6f f1             	movq   mm6,mm1
  12:	0f 6f f9             	movq   mm7,mm1
  15:	0f 6f c1             	movq   mm0,mm1
  18:	0f 6f d1             	movq   mm2,mm1
  1b:	0f 6f d9             	movq   mm3,mm1
  1e:	0f 6f e1             	movq   mm4,mm1
  21:	0f 6f e9             	movq   mm5,mm1
  24:	0f 6f f1             	movq   mm6,mm1
  27:	0f 6f f9             	movq   mm7,mm1
  2a:	0f 6f c1             	movq   mm0,mm1
  2d:	0f 6f d1             	movq   mm2,mm1
  30:	41 f7 2e             	imul   DWORD PTR [r14]

Init:
```
PXOR MM1, MM1
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.11
- Reference cycles: 4.71
- UOPS_PORT_0: 7.97
- UOPS_PORT_5: 8.02

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 41 c1 c0 00       	rol    r8w,0x0
  26:	66 41 c1 c1 00       	rol    r9w,0x0
  2b:	66 41 c1 c2 00       	rol    r10w,0x0
  30:	66 41 c1 c3 00       	rol    r11w,0x0
  35:	66 41 c1 c4 00       	rol    r12w,0x0
  3a:	66 c1 c3 00          	rol    bx,0x0
  3e:	66 c1 c1 00          	rol    cx,0x0
  42:	66 41 c1 c0 00       	rol    r8w,0x0
  47:	66 41 c1 c1 00       	rol    r9w,0x0
  4c:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.53
- Reference cycles: 4.71
- UOPS_PORT_6: 8.5
- UOPS_PORT_0: 8.5

⇨ One μop that can only use ports {'0', '6'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	66 0f 55 f9          	andnpd xmm7,xmm1
  51:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  56:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  5b:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  60:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  65:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  6a:	41 f7 2e             	imul   DWORD PTR [r14]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 8.59
- Reference cycles: 5.94
- UOPS_PORT_1: 8.37
- UOPS_PORT_0: 8.32
- UOPS_PORT_5: 8.32

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 8d 46 08          	lea    r8d,[r14+0x8]
   4:	45 8d 4e 08          	lea    r9d,[r14+0x8]
   8:	45 8d 56 08          	lea    r10d,[r14+0x8]
   c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  10:	45 8d 66 08          	lea    r12d,[r14+0x8]
  14:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  18:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  1c:	45 8d 46 08          	lea    r8d,[r14+0x8]
  20:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  24:	45 8d 56 08          	lea    r10d,[r14+0x8]
  28:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  2c:	45 8d 66 08          	lea    r12d,[r14+0x8]
  30:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  34:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  38:	45 8d 46 08          	lea    r8d,[r14+0x8]
  3c:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  40:	45 8d 56 08          	lea    r10d,[r14+0x8]
  44:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  48:	45 8d 66 08          	lea    r12d,[r14+0x8]
  4c:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  50:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  54:	45 8d 46 08          	lea    r8d,[r14+0x8]
  58:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  5c:	45 8d 56 08          	lea    r10d,[r14+0x8]
  60:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  64:	45 8d 66 08          	lea    r12d,[r14+0x8]
  68:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  6c:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  70:	45 8d 46 08          	lea    r8d,[r14+0x8]
  74:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  78:	45 8d 56 08          	lea    r10d,[r14+0x8]
  7c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  80:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 33.0
- Core cycles: 9.29
- Reference cycles: 7.06
- UOPS_PORT_1: 8.13
- UOPS_PORT_0: 8.94
- UOPS_PORT_6: 9.0
- UOPS_PORT_5: 8.94

⇨ One μop that can only use ports {'0', '1', '5', '6'}

With an indexed addressing mode

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
   7:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
   e:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  15:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  1c:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  23:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  2a:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  31:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  38:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  3f:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  46:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.09
- Reference cycles: 7.67
- UOPS_PORT_1: 10.98

⇨ One μop that can only use port '1'

With blocking instructions for port '23':

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.73
- Reference cycles: 4.91
- UOPS_PORT_23: 17.0

⇨ One μop that can only use port '23'

With blocking instructions for ports {'0', '5'}:

Code:

   0:	0f 6f c1             	movq   mm0,mm1
   3:	0f 6f d1             	movq   mm2,mm1
   6:	0f 6f d9             	movq   mm3,mm1
   9:	0f 6f e1             	movq   mm4,mm1
   c:	0f 6f e9             	movq   mm5,mm1
   f:	0f 6f f1             	movq   mm6,mm1
  12:	0f 6f f9             	movq   mm7,mm1
  15:	0f 6f c1             	movq   mm0,mm1
  18:	0f 6f d1             	movq   mm2,mm1
  1b:	0f 6f d9             	movq   mm3,mm1
  1e:	0f 6f e1             	movq   mm4,mm1
  21:	0f 6f e9             	movq   mm5,mm1
  24:	0f 6f f1             	movq   mm6,mm1
  27:	0f 6f f9             	movq   mm7,mm1
  2a:	0f 6f c1             	movq   mm0,mm1
  2d:	0f 6f d1             	movq   mm2,mm1
  30:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
PXOR MM1, MM1;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.19
- Reference cycles: 4.71
- UOPS_PORT_0: 8.0
- UOPS_PORT_5: 7.98

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 41 c1 c0 00       	rol    r8w,0x0
  26:	66 41 c1 c1 00       	rol    r9w,0x0
  2b:	66 41 c1 c2 00       	rol    r10w,0x0
  30:	66 41 c1 c3 00       	rol    r11w,0x0
  35:	66 41 c1 c4 00       	rol    r12w,0x0
  3a:	66 c1 c3 00          	rol    bx,0x0
  3e:	66 c1 c1 00          	rol    cx,0x0
  42:	66 41 c1 c0 00       	rol    r8w,0x0
  47:	66 41 c1 c1 00       	rol    r9w,0x0
  4c:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.6
- Reference cycles: 4.71
- UOPS_PORT_6: 8.5
- UOPS_PORT_0: 8.48

⇨ One μop that can only use ports {'0', '6'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	66 0f 55 f9          	andnpd xmm7,xmm1
  51:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  56:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  5b:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  60:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  65:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  6a:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 8.61
- Reference cycles: 5.34
- UOPS_PORT_1: 8.34
- UOPS_PORT_0: 8.32
- UOPS_PORT_5: 8.32

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 8d 46 08          	lea    r8d,[r14+0x8]
   4:	45 8d 4e 08          	lea    r9d,[r14+0x8]
   8:	45 8d 56 08          	lea    r10d,[r14+0x8]
   c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  10:	45 8d 66 08          	lea    r12d,[r14+0x8]
  14:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  18:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  1c:	45 8d 46 08          	lea    r8d,[r14+0x8]
  20:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  24:	45 8d 56 08          	lea    r10d,[r14+0x8]
  28:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  2c:	45 8d 66 08          	lea    r12d,[r14+0x8]
  30:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  34:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  38:	45 8d 46 08          	lea    r8d,[r14+0x8]
  3c:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  40:	45 8d 56 08          	lea    r10d,[r14+0x8]
  44:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  48:	45 8d 66 08          	lea    r12d,[r14+0x8]
  4c:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  50:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  54:	45 8d 46 08          	lea    r8d,[r14+0x8]
  58:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  5c:	45 8d 56 08          	lea    r10d,[r14+0x8]
  60:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  64:	45 8d 66 08          	lea    r12d,[r14+0x8]
  68:	41 8d 5e 08          	lea    ebx,[r14+0x8]
  6c:	41 8d 4e 08          	lea    ecx,[r14+0x8]
  70:	45 8d 46 08          	lea    r8d,[r14+0x8]
  74:	45 8d 4e 08          	lea    r9d,[r14+0x8]
  78:	45 8d 56 08          	lea    r10d,[r14+0x8]
  7c:	45 8d 5e 08          	lea    r11d,[r14+0x8]
  80:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 33.0
- Core cycles: 9.35
- Reference cycles: 4.71
- UOPS_PORT_1: 8.16
- UOPS_PORT_0: 9.0
- UOPS_PORT_6: 8.94
- UOPS_PORT_5: 8.9

⇨ One μop that can only use ports {'0', '1', '5', '6'}