IMUL (M32) - Latency


Operands


Latency operand 1 → 2 (address, base register): 7

Latency operand 1 → 2 (address, index register): 7

Latency operand 1 → 2 (memory): ≤9

Latency operand 1 → 3 (address, base register): 8

Latency operand 1 → 3 (address, index register): 8

Latency operand 1 → 3 (memory): ≤9

Latency operand 1 → 4 (address, base register): 6

Latency operand 1 → 4 (address, index register): 6

Latency operand 1 → 4 (memory): ≤7

Latency operand 2 → 2: 4

Latency operand 2 → 3: 4

Latency operand 2 → 4: 4


Latency operand 1 → 2 (address, base register): 7

Experiment 1


Latency operand 1 → 2 (address, index register): 7

Experiment 1


Latency operand 1 → 2 (memory): ≤9

Experiment 1


Latency operand 1 → 3 (address, base register): 8

Experiment 1


Latency operand 1 → 3 (address, index register): 8

Experiment 1


Latency operand 1 → 3 (memory): ≤9

Experiment 1


Latency operand 1 → 4 (address, base register): 6

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)


Latency operand 1 → 4 (address, index register): 6

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)


Latency operand 1 → 4 (memory): ≤7

Experiment 1

Experiment 2


Latency operand 2 → 2: 4

Experiment 1

Experiment 2


Latency operand 2 → 3: 4

Experiment 1


Latency operand 2 → 4: 4

Experiment 1

Experiment 2