IMUL (M32)

With unroll_count=500 and no inner loop

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.75
- Reference cycles: 4.75
- RS_UOPS_DISPATCHED: 4.0
- UOPS_PORT_0: 0.91
- UOPS_PORT_1: 1.01
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.08

With loop_count=1000 and unroll_count=10

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.7
- Reference cycles: 4.7
- RS_UOPS_DISPATCHED: 4.2
- UOPS_PORT_0: 1.03
- UOPS_PORT_1: 1.05
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.12

With loop_count=100 and unroll_count=100

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.74
- Reference cycles: 4.74
- RS_UOPS_DISPATCHED: 4.02
- UOPS_PORT_0: 0.93
- UOPS_PORT_1: 1.01
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.08

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.5
- Reference cycles: 1.51
- RS_UOPS_DISPATCHED: 5.0
- UOPS_PORT_0: 1.29
- UOPS_PORT_1: 1.32
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.39

With loop_count=1000 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 1.59
- Reference cycles: 1.59
- RS_UOPS_DISPATCHED: 5.2
- UOPS_PORT_0: 1.36
- UOPS_PORT_1: 1.38
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.46

With loop_count=100 and unroll_count=100

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 1.52
- Reference cycles: 1.52
- RS_UOPS_DISPATCHED: 5.02
- UOPS_PORT_0: 1.31
- UOPS_PORT_1: 1.32
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.39

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 19.0
- Reference cycles: 18.99
- RS_UOPS_DISPATCHED: 16.0
- UOPS_PORT_0: 3.65
- UOPS_PORT_1: 4.02
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.33

With loop_count=1000 and unroll_count=2

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 18.88
- Reference cycles: 18.88
- RS_UOPS_DISPATCHED: 17.0
- UOPS_PORT_0: 3.88
- UOPS_PORT_1: 4.47
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.66

With loop_count=100 and unroll_count=20

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 18.95
- Reference cycles: 18.95
- RS_UOPS_DISPATCHED: 16.1
- UOPS_PORT_0: 3.73
- UOPS_PORT_1: 4.08
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.29

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 5.98
- Reference cycles: 5.97
- RS_UOPS_DISPATCHED: 20.0
- UOPS_PORT_0: 5.17
- UOPS_PORT_1: 5.3
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.54

With loop_count=1000 and unroll_count=2

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 6.42
- Reference cycles: 6.42
- RS_UOPS_DISPATCHED: 21.02
- UOPS_PORT_0: 5.48
- UOPS_PORT_1: 5.57
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.96

With loop_count=100 and unroll_count=20

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 8.1
- Core cycles: 6.13
- Reference cycles: 6.13
- RS_UOPS_DISPATCHED: 20.11
- UOPS_PORT_0: 5.24
- UOPS_PORT_1: 5.3
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.57

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 38.0
- Reference cycles: 38.01
- RS_UOPS_DISPATCHED: 32.0
- UOPS_PORT_0: 7.3
- UOPS_PORT_1: 8.04
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.66

With loop_count=1000 and unroll_count=1

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 37.76
- Reference cycles: 37.75
- RS_UOPS_DISPATCHED: 34.0
- UOPS_PORT_0: 7.76
- UOPS_PORT_1: 8.94
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 9.31

With loop_count=100 and unroll_count=10

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 37.91
- Reference cycles: 37.91
- RS_UOPS_DISPATCHED: 32.2
- UOPS_PORT_0: 7.46
- UOPS_PORT_1: 8.15
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.59

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 12.17
- Reference cycles: 12.16
- RS_UOPS_DISPATCHED: 40.0
- UOPS_PORT_0: 10.47
- UOPS_PORT_1: 10.57
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 10.96

With loop_count=1000 and unroll_count=1

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 12.85
- Reference cycles: 12.84
- RS_UOPS_DISPATCHED: 42.04
- UOPS_PORT_0: 10.97
- UOPS_PORT_1: 11.15
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 11.92

With loop_count=100 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 12.2
- Reference cycles: 12.19
- RS_UOPS_DISPATCHED: 40.23
- UOPS_PORT_0: 10.52
- UOPS_PORT_1: 10.61
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 11.1

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  1f:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  23:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  27:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  2b:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  2f:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  33:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  37:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  3b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 76.0
- Reference cycles: 76.04
- RS_UOPS_DISPATCHED: 64.0
- UOPS_PORT_0: 14.7
- UOPS_PORT_1: 15.96
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 17.34

With loop_count=1000 and unroll_count=1

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  1f:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  23:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  27:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  2b:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  2f:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  33:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  37:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  3b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 75.55
- Reference cycles: 75.55
- RS_UOPS_DISPATCHED: 66.0
- UOPS_PORT_0: 15.73
- UOPS_PORT_1: 17.18
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 17.09

With loop_count=100 and unroll_count=10

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  1f:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  23:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  27:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  2b:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  2f:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  33:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  37:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  3b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 75.92
- Reference cycles: 75.91
- RS_UOPS_DISPATCHED: 64.2
- UOPS_PORT_0: 14.85
- UOPS_PORT_1: 16.14
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 17.21

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  37:	48 31 c0             	xor    rax,rax
  3a:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  3e:	48 31 c0             	xor    rax,rax
  41:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  45:	48 31 c0             	xor    rax,rax
  48:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  4c:	48 31 c0             	xor    rax,rax
  4f:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  53:	48 31 c0             	xor    rax,rax
  56:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  5a:	48 31 c0             	xor    rax,rax
  5d:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  61:	48 31 c0             	xor    rax,rax
  64:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  68:	48 31 c0             	xor    rax,rax
  6b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 32.0
- Core cycles: 25.16
- Reference cycles: 25.15
- RS_UOPS_DISPATCHED: 80.0
- UOPS_PORT_0: 20.6
- UOPS_PORT_1: 21.32
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 22.08

With loop_count=1000 and unroll_count=1

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  37:	48 31 c0             	xor    rax,rax
  3a:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  3e:	48 31 c0             	xor    rax,rax
  41:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  45:	48 31 c0             	xor    rax,rax
  48:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  4c:	48 31 c0             	xor    rax,rax
  4f:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  53:	48 31 c0             	xor    rax,rax
  56:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  5a:	48 31 c0             	xor    rax,rax
  5d:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  61:	48 31 c0             	xor    rax,rax
  64:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  68:	48 31 c0             	xor    rax,rax
  6b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 34.0
- Core cycles: 24.94
- Reference cycles: 24.93
- RS_UOPS_DISPATCHED: 82.03
- UOPS_PORT_0: 21.43
- UOPS_PORT_1: 21.75
- UOPS_PORT_2: 16.01
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 22.85

With loop_count=100 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  37:	48 31 c0             	xor    rax,rax
  3a:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  3e:	48 31 c0             	xor    rax,rax
  41:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  45:	48 31 c0             	xor    rax,rax
  48:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  4c:	48 31 c0             	xor    rax,rax
  4f:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  53:	48 31 c0             	xor    rax,rax
  56:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  5a:	48 31 c0             	xor    rax,rax
  5d:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  61:	48 31 c0             	xor    rax,rax
  64:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  68:	48 31 c0             	xor    rax,rax
  6b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 32.2
- Core cycles: 24.4
- Reference cycles: 24.4
- RS_UOPS_DISPATCHED: 80.23
- UOPS_PORT_0: 20.9
- UOPS_PORT_1: 21.11
- UOPS_PORT_2: 16.01
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 22.22

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.75
- Reference cycles: 4.75
- RS_UOPS_DISPATCHED: 4.0
- UOPS_PORT_0: 0.91
- UOPS_PORT_1: 1.01
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.08

With loop_count=1000 and unroll_count=10

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.7
- Reference cycles: 4.7
- RS_UOPS_DISPATCHED: 4.2
- UOPS_PORT_0: 1.03
- UOPS_PORT_1: 1.05
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.12

With loop_count=100 and unroll_count=100

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.74
- Reference cycles: 4.74
- RS_UOPS_DISPATCHED: 4.02
- UOPS_PORT_0: 0.93
- UOPS_PORT_1: 1.01
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.08

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.51
- Reference cycles: 1.51
- RS_UOPS_DISPATCHED: 5.0
- UOPS_PORT_0: 1.3
- UOPS_PORT_1: 1.31
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.39

With loop_count=1000 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 1.59
- Reference cycles: 1.59
- RS_UOPS_DISPATCHED: 5.2
- UOPS_PORT_0: 1.36
- UOPS_PORT_1: 1.38
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.46

With loop_count=100 and unroll_count=100

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 1.53
- Reference cycles: 1.53
- RS_UOPS_DISPATCHED: 5.02
- UOPS_PORT_0: 1.31
- UOPS_PORT_1: 1.32
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 1.39

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 19.0
- Reference cycles: 18.99
- RS_UOPS_DISPATCHED: 16.0
- UOPS_PORT_0: 3.65
- UOPS_PORT_1: 4.02
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.33

With loop_count=1000 and unroll_count=2

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 18.88
- Reference cycles: 18.88
- RS_UOPS_DISPATCHED: 17.0
- UOPS_PORT_0: 3.88
- UOPS_PORT_1: 4.47
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.66

With loop_count=100 and unroll_count=20

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 18.95
- Reference cycles: 18.96
- RS_UOPS_DISPATCHED: 16.1
- UOPS_PORT_0: 3.73
- UOPS_PORT_1: 4.08
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 4.29

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 6.11
- Reference cycles: 6.12
- RS_UOPS_DISPATCHED: 20.0
- UOPS_PORT_0: 5.18
- UOPS_PORT_1: 5.28
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.55

With loop_count=1000 and unroll_count=2

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 6.42
- Reference cycles: 6.42
- RS_UOPS_DISPATCHED: 21.02
- UOPS_PORT_0: 5.49
- UOPS_PORT_1: 5.56
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.96

With loop_count=100 and unroll_count=20

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.1
- Core cycles: 6.13
- Reference cycles: 6.13
- RS_UOPS_DISPATCHED: 20.11
- UOPS_PORT_0: 5.26
- UOPS_PORT_1: 5.31
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 5.55

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 38.0
- Reference cycles: 38.01
- RS_UOPS_DISPATCHED: 32.0
- UOPS_PORT_0: 7.3
- UOPS_PORT_1: 8.04
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.66

With loop_count=1000 and unroll_count=1

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 37.76
- Reference cycles: 37.76
- RS_UOPS_DISPATCHED: 34.0
- UOPS_PORT_0: 7.76
- UOPS_PORT_1: 8.94
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 9.31

With loop_count=100 and unroll_count=10

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 37.91
- Reference cycles: 37.91
- RS_UOPS_DISPATCHED: 32.2
- UOPS_PORT_0: 7.46
- UOPS_PORT_1: 8.15
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 8.59

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 12.24
- Reference cycles: 12.24
- RS_UOPS_DISPATCHED: 40.0
- UOPS_PORT_0: 10.3
- UOPS_PORT_1: 10.6
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 11.1

With loop_count=1000 and unroll_count=1

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 12.83
- Reference cycles: 12.84
- RS_UOPS_DISPATCHED: 42.03
- UOPS_PORT_0: 10.98
- UOPS_PORT_1: 11.12
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 11.93

With loop_count=100 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 12.24
- Reference cycles: 12.25
- RS_UOPS_DISPATCHED: 40.23
- UOPS_PORT_0: 10.52
- UOPS_PORT_1: 10.61
- UOPS_PORT_2: 8.01
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 11.09

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  27:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  2c:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  31:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  36:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  3b:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  40:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  45:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  4a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 76.0
- Reference cycles: 76.0
- RS_UOPS_DISPATCHED: 64.0
- UOPS_PORT_0: 14.7
- UOPS_PORT_1: 15.96
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 17.34

With loop_count=1000 and unroll_count=1

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  27:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  2c:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  31:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  36:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  3b:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  40:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  45:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  4a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 75.55
- Reference cycles: 75.56
- RS_UOPS_DISPATCHED: 66.0
- UOPS_PORT_0: 15.73
- UOPS_PORT_1: 17.18
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 17.09

With loop_count=100 and unroll_count=10

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  27:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  2c:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  31:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  36:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  3b:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  40:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  45:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  4a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 75.92
- Reference cycles: 75.92
- RS_UOPS_DISPATCHED: 64.2
- UOPS_PORT_0: 14.85
- UOPS_PORT_1: 16.14
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 17.21

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  3f:	48 31 c0             	xor    rax,rax
  42:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  47:	48 31 c0             	xor    rax,rax
  4a:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  4f:	48 31 c0             	xor    rax,rax
  52:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  57:	48 31 c0             	xor    rax,rax
  5a:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  5f:	48 31 c0             	xor    rax,rax
  62:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  67:	48 31 c0             	xor    rax,rax
  6a:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  6f:	48 31 c0             	xor    rax,rax
  72:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  77:	48 31 c0             	xor    rax,rax
  7a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 32.0
- Core cycles: 24.9
- Reference cycles: 24.89
- RS_UOPS_DISPATCHED: 80.0
- UOPS_PORT_0: 20.41
- UOPS_PORT_1: 21.26
- UOPS_PORT_2: 16.0
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 22.33

With loop_count=1000 and unroll_count=1

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  3f:	48 31 c0             	xor    rax,rax
  42:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  47:	48 31 c0             	xor    rax,rax
  4a:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  4f:	48 31 c0             	xor    rax,rax
  52:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  57:	48 31 c0             	xor    rax,rax
  5a:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  5f:	48 31 c0             	xor    rax,rax
  62:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  67:	48 31 c0             	xor    rax,rax
  6a:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  6f:	48 31 c0             	xor    rax,rax
  72:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  77:	48 31 c0             	xor    rax,rax
  7a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 34.0
- Core cycles: 24.94
- Reference cycles: 24.94
- RS_UOPS_DISPATCHED: 82.03
- UOPS_PORT_0: 21.43
- UOPS_PORT_1: 21.75
- UOPS_PORT_2: 16.01
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 22.85

With loop_count=100 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  3f:	48 31 c0             	xor    rax,rax
  42:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  47:	48 31 c0             	xor    rax,rax
  4a:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  4f:	48 31 c0             	xor    rax,rax
  52:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  57:	48 31 c0             	xor    rax,rax
  5a:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  5f:	48 31 c0             	xor    rax,rax
  62:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  67:	48 31 c0             	xor    rax,rax
  6a:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  6f:	48 31 c0             	xor    rax,rax
  72:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  77:	48 31 c0             	xor    rax,rax
  7a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 32.2
- Core cycles: 24.38
- Reference cycles: 24.38
- RS_UOPS_DISPATCHED: 80.23
- UOPS_PORT_0: 20.89
- UOPS_PORT_1: 21.12
- UOPS_PORT_2: 16.01
- UOPS_PORT_3: 0.0
- UOPS_PORT_4: 0.0
- UOPS_PORT_5: 22.22

IMUL (M32) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10