IMUL (M32) - Port Usage

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
   7:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
   e:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  15:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  1c:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  23:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  2a:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  31:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  38:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  3f:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  46:	41 f7 2e             	imul   DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.03
- Reference cycles: 8.32
- UOPS_PORT_1: 11.01

⇨ One μop that can only use port '1'

With blocking instructions for port '23A':

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	41 f7 2e             	imul   DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 8.63
- Reference cycles: 7.41
- UOPS_PORT_23A: 25.0

⇨ One μop that can only use port '23A'

With blocking instructions for port '5':

Code:

   0:	66 0f 3a 21 c1 02    	insertps xmm0,xmm1,0x2
   6:	66 0f 3a 21 d1 02    	insertps xmm2,xmm1,0x2
   c:	66 0f 3a 21 d9 02    	insertps xmm3,xmm1,0x2
  12:	66 0f 3a 21 e1 02    	insertps xmm4,xmm1,0x2
  18:	66 0f 3a 21 e9 02    	insertps xmm5,xmm1,0x2
  1e:	66 0f 3a 21 f1 02    	insertps xmm6,xmm1,0x2
  24:	66 0f 3a 21 f9 02    	insertps xmm7,xmm1,0x2
  2a:	66 44 0f 3a 21 c1 02 	insertps xmm8,xmm1,0x2
  31:	66 44 0f 3a 21 c9 02 	insertps xmm9,xmm1,0x2
  38:	66 44 0f 3a 21 d1 02 	insertps xmm10,xmm1,0x2
  3f:	41 f7 2e             	imul   DWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.01
- Reference cycles: 7.36
- UOPS_PORT_5B: 10.43
- UOPS_PORT_5B>=2: 0.43

With blocking instructions for ports {'0', '5'}:

Code:

   0:	0f 6f c1             	movq   mm0,mm1
   3:	0f 6f d1             	movq   mm2,mm1
   6:	0f 6f d9             	movq   mm3,mm1
   9:	0f 6f e1             	movq   mm4,mm1
   c:	0f 6f e9             	movq   mm5,mm1
   f:	0f 6f f1             	movq   mm6,mm1
  12:	0f 6f f9             	movq   mm7,mm1
  15:	0f 6f c1             	movq   mm0,mm1
  18:	0f 6f d1             	movq   mm2,mm1
  1b:	0f 6f d9             	movq   mm3,mm1
  1e:	0f 6f e1             	movq   mm4,mm1
  21:	0f 6f e9             	movq   mm5,mm1
  24:	0f 6f f1             	movq   mm6,mm1
  27:	0f 6f f9             	movq   mm7,mm1
  2a:	0f 6f c1             	movq   mm0,mm1
  2d:	0f 6f d1             	movq   mm2,mm1
  30:	41 f7 2e             	imul   DWORD PTR [r14]

Init:
```
PXOR MM1, MM1
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.07
- Reference cycles: 5.68
- UOPS_PORT_0: 8.02
- UOPS_PORT_5B: 8.52
- UOPS_PORT_5B>=2: 0.5

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 41 c1 c0 00       	rol    r8w,0x0
  26:	66 41 c1 c1 00       	rol    r9w,0x0
  2b:	66 41 c1 c2 00       	rol    r10w,0x0
  30:	66 41 c1 c3 00       	rol    r11w,0x0
  35:	66 41 c1 c4 00       	rol    r12w,0x0
  3a:	66 c1 c3 00          	rol    bx,0x0
  3e:	66 c1 c1 00          	rol    cx,0x0
  42:	66 41 c1 c0 00       	rol    r8w,0x0
  47:	66 41 c1 c1 00       	rol    r9w,0x0
  4c:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.59
- Reference cycles: 6.71
- UOPS_PORT_6: 8.49
- UOPS_PORT_0: 8.51

⇨ One μop that can only use ports {'0', '6'}

With blocking instructions for ports {'1', '5'}:

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	66 44 0f 58 d9       	addpd  xmm11,xmm1
  30:	66 44 0f 58 e1       	addpd  xmm12,xmm1
  35:	66 0f 58 c1          	addpd  xmm0,xmm1
  39:	66 0f 58 d1          	addpd  xmm2,xmm1
  3d:	66 0f 58 d9          	addpd  xmm3,xmm1
  41:	66 0f 58 e1          	addpd  xmm4,xmm1
  45:	41 f7 2e             	imul   DWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.58
- Reference cycles: 6.19
- UOPS_PORT_1: 8.5
- UOPS_PORT_5B: 9.03
- UOPS_PORT_5B>=2: 0.53

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  30:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  35:	66 0f 55 c1          	andnpd xmm0,xmm1
  39:	66 0f 55 d1          	andnpd xmm2,xmm1
  3d:	66 0f 55 d9          	andnpd xmm3,xmm1
  41:	66 0f 55 e1          	andnpd xmm4,xmm1
  45:	66 0f 55 e9          	andnpd xmm5,xmm1
  49:	66 0f 55 f1          	andnpd xmm6,xmm1
  4d:	66 0f 55 f9          	andnpd xmm7,xmm1
  51:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  56:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  5b:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  60:	66 44 0f 55 d9       	andnpd xmm11,xmm1
  65:	66 44 0f 55 e1       	andnpd xmm12,xmm1
  6a:	41 f7 2e             	imul   DWORD PTR [r14]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 8.46
- Reference cycles: 5.46
- UOPS_PORT_1: 8.37
- UOPS_PORT_0: 8.32
- UOPS_PORT_5B: 9.32
- UOPS_PORT_5B>=2: 0.98

With blocking instructions for ports {'0', '5', '6'}:

Code:

   0:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
   4:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
   8:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
   c:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  10:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  14:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  18:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  1c:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  20:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  24:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  28:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  2c:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  30:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  34:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  38:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  3c:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  40:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  44:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  48:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  4c:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  50:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  54:	47 8d 04 6e          	lea    r8d,[r14+r13*2]
  58:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  5c:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  60:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 8.41
- Reference cycles: 6.24
- UOPS_PORT_6: 8.34
- UOPS_PORT_0: 8.34
- UOPS_PORT_5B: 9.09
- UOPS_PORT_5B>=2: 0.77

With blocking instructions for ports {'1', '5', 'B'}:

Code:

   0:	66 45 0f be c1       	movsx  r8w,r9b
   5:	66 45 0f be d1       	movsx  r10w,r9b
   a:	66 45 0f be d9       	movsx  r11w,r9b
   f:	66 45 0f be e1       	movsx  r12w,r9b
  14:	66 41 0f be d9       	movsx  bx,r9b
  19:	66 41 0f be c9       	movsx  cx,r9b
  1e:	66 45 0f be c1       	movsx  r8w,r9b
  23:	66 45 0f be d1       	movsx  r10w,r9b
  28:	66 45 0f be d9       	movsx  r11w,r9b
  2d:	66 45 0f be e1       	movsx  r12w,r9b
  32:	66 41 0f be d9       	movsx  bx,r9b
  37:	66 41 0f be c9       	movsx  cx,r9b
  3c:	66 45 0f be c1       	movsx  r8w,r9b
  41:	66 45 0f be d1       	movsx  r10w,r9b
  46:	66 45 0f be d9       	movsx  r11w,r9b
  4b:	66 45 0f be e1       	movsx  r12w,r9b
  50:	66 41 0f be d9       	movsx  bx,r9b
  55:	66 41 0f be c9       	movsx  cx,r9b
  5a:	66 45 0f be c1       	movsx  r8w,r9b
  5f:	66 45 0f be d1       	movsx  r10w,r9b
  64:	66 45 0f be d9       	movsx  r11w,r9b
  69:	66 45 0f be e1       	movsx  r12w,r9b
  6e:	66 41 0f be d9       	movsx  bx,r9b
  73:	66 41 0f be c9       	movsx  cx,r9b
  78:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 9.05
- Reference cycles: 7.41
- UOPS_PORT_1: 8.05
- UOPS_PORT_5B: 16.95

With blocking instructions for ports {'0', '1', '5', '6', 'B'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	45 8d 06             	lea    r8d,[r14]
  18:	45 8d 0e             	lea    r9d,[r14]
  1b:	45 8d 16             	lea    r10d,[r14]
  1e:	45 8d 1e             	lea    r11d,[r14]
  21:	45 8d 26             	lea    r12d,[r14]
  24:	41 8d 1e             	lea    ebx,[r14]
  27:	41 8d 0e             	lea    ecx,[r14]
  2a:	45 8d 06             	lea    r8d,[r14]
  2d:	45 8d 0e             	lea    r9d,[r14]
  30:	45 8d 16             	lea    r10d,[r14]
  33:	45 8d 1e             	lea    r11d,[r14]
  36:	45 8d 26             	lea    r12d,[r14]
  39:	41 8d 1e             	lea    ebx,[r14]
  3c:	41 8d 0e             	lea    ecx,[r14]
  3f:	45 8d 06             	lea    r8d,[r14]
  42:	45 8d 0e             	lea    r9d,[r14]
  45:	45 8d 16             	lea    r10d,[r14]
  48:	45 8d 1e             	lea    r11d,[r14]
  4b:	45 8d 26             	lea    r12d,[r14]
  4e:	41 8d 1e             	lea    ebx,[r14]
  51:	41 8d 0e             	lea    ecx,[r14]
  54:	45 8d 06             	lea    r8d,[r14]
  57:	45 8d 0e             	lea    r9d,[r14]
  5a:	45 8d 16             	lea    r10d,[r14]
  5d:	45 8d 1e             	lea    r11d,[r14]
  60:	45 8d 26             	lea    r12d,[r14]
  63:	41 8d 1e             	lea    ebx,[r14]
  66:	41 8d 0e             	lea    ecx,[r14]
  69:	45 8d 06             	lea    r8d,[r14]
  6c:	45 8d 0e             	lea    r9d,[r14]
  6f:	45 8d 16             	lea    r10d,[r14]
  72:	45 8d 1e             	lea    r11d,[r14]
  75:	45 8d 26             	lea    r12d,[r14]
  78:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 41.0
- Core cycles: 8.99
- Reference cycles: 6.4
- UOPS_PORT_6: 8.77
- UOPS_PORT_0: 8.71
- UOPS_PORT_1: 7.92
- UOPS_PORT_5B: 17.57

⇨ One μop that can only use ports {'0', '1', '5', '6', 'B'}

With an indexed addressing mode

With blocking instructions for port '1':

Code:

   0:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
   7:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
   e:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  15:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  1c:	66 f2 41 0f 38 f1 d9 	crc32  ebx,r9w
  23:	66 f2 41 0f 38 f1 c9 	crc32  ecx,r9w
  2a:	66 f2 45 0f 38 f1 c1 	crc32  r8d,r9w
  31:	66 f2 45 0f 38 f1 d1 	crc32  r10d,r9w
  38:	66 f2 45 0f 38 f1 d9 	crc32  r11d,r9w
  3f:	66 f2 45 0f 38 f1 e1 	crc32  r12d,r9w
  46:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.03
- Reference cycles: 8.16
- UOPS_PORT_1: 11.01

⇨ One μop that can only use port '1'

With blocking instructions for port '23A':

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  81:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  88:	00 00 
  8a:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  91:	00 00 
  93:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  9a:	00 00 
  9c:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  a3:	00 00 
  a5:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  ac:	00 00 
  ae:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  b5:	00 00 
  b7:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  be:	00 00 
  c0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 8.68
- Reference cycles: 6.63
- UOPS_PORT_23A: 25.0

⇨ One μop that can only use port '23A'

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 41 c1 c0 00       	rol    r8w,0x0
  26:	66 41 c1 c1 00       	rol    r9w,0x0
  2b:	66 41 c1 c2 00       	rol    r10w,0x0
  30:	66 41 c1 c3 00       	rol    r11w,0x0
  35:	66 41 c1 c4 00       	rol    r12w,0x0
  3a:	66 c1 c3 00          	rol    bx,0x0
  3e:	66 c1 c1 00          	rol    cx,0x0
  42:	66 41 c1 c0 00       	rol    r8w,0x0
  47:	66 41 c1 c1 00       	rol    r9w,0x0
  4c:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.58
- Reference cycles: 6.19
- UOPS_PORT_6: 8.45
- UOPS_PORT_0: 8.52

⇨ One μop that can only use ports {'0', '6'}