IMUL (M32) - Throughput and Uops (IACA 3.0)


With a non-indexed addressing mode

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 3.00 Cycles       Throughput Bottleneck: Dependency chains
Loop Count:  60
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  |  1.0  |  0.5     0.5  |  0.5     0.5  |  0.0  |  0.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   2      |             | 1.0  | 0.5     0.5 | 0.5     0.5 |      |      |      |      | imul dword ptr [r14]
Total Num Of Uops: 2

With additional dependency-breaking instructions

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: Dependency chains
Loop Count:  30
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  |  1.0  |  0.5     0.5  |  0.5     0.5  |  0.0  |  0.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   2      |             | 1.0  | 0.5     0.5 | 0.5     0.5 |      |      |      |      | imul dword ptr [r14]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
Total Num Of Uops: 3

With 16 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 48.00 Cycles       Throughput Bottleneck: Backend
Loop Count:  22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  | 16.0  |  8.0     8.0  |  8.0     8.0  |  0.0  |  0.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x4]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x8]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0xc]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x10]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x14]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x18]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x1c]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x20]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x24]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x28]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x2c]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x30]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x34]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x38]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x3c]
Total Num Of Uops: 32

With additional dependency-breaking instructions

Throughput Analysis Report
--------------------------
Block Throughput: 16.00 Cycles       Throughput Bottleneck: Backend
Loop Count:  22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  | 16.0  |  8.0     8.0  |  8.0     8.0  |  0.0  |  0.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x4]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x8]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0xc]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x10]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x14]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x18]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x1c]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x20]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x24]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x28]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x2c]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x30]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x34]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+0x38]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+0x3c]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
Total Num Of Uops: 48

With an indexed addressing mode

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 3.00 Cycles       Throughput Bottleneck: Dependency chains
Loop Count:  60
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  |  1.0  |  0.5     0.5  |  0.5     0.5  |  0.0  |  0.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   2      |             | 1.0  | 0.5     0.5 | 0.5     0.5 |      |      |      |      | imul dword ptr [r14+r13*1]
Total Num Of Uops: 2

With additional dependency-breaking instructions

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: Dependency chains
Loop Count:  30
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  |  1.0  |  0.5     0.5  |  0.5     0.5  |  0.0  |  0.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   2      |             | 1.0  | 0.5     0.5 | 0.5     0.5 |      |      |      |      | imul dword ptr [r14+r13*1]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
Total Num Of Uops: 3

With 16 independent instructions


Throughput Analysis Report
--------------------------
Block Throughput: 48.00 Cycles       Throughput Bottleneck: Backend
Loop Count:  22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  | 16.0  |  8.0     8.0  |  8.0     8.0  |  0.0  |  0.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x4]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x8]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0xc]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x10]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x14]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x18]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x1c]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x20]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x24]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x28]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x2c]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x30]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x34]
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x38]
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x3c]
Total Num Of Uops: 32

With additional dependency-breaking instructions

Throughput Analysis Report
--------------------------
Block Throughput: 16.00 Cycles       Throughput Bottleneck: Backend
Loop Count:  22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
|  Port  |   0   -  DV   |   1   |   2   -  D    |   3   -  D    |   4   |   5   |   6   |   7   |
--------------------------------------------------------------------------------------------------
| Cycles |  0.0     0.0  | 16.0  |  8.0     8.0  |  8.0     8.0  |  0.0  |  0.0  |  0.0  |  0.0  |
--------------------------------------------------------------------------------------------------

| Num Of   |                    Ports pressure in cycles                         |      |
|  Uops    |  0  - DV    |  1   |  2  -  D    |  3  -  D    |  4   |  5   |  6   |  7   |
-----------------------------------------------------------------------------------------
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x4]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x8]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0xc]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x10]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x14]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x18]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x1c]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x20]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x24]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x28]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x2c]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x30]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x34]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  | 1.0     1.0 |             |      |      |      |      | imul dword ptr [r14+r13*1+0x38]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
|   2      |             | 1.0  |             | 1.0     1.0 |      |      |      |      | imul dword ptr [r14+r13*1+0x3c]
|   1*     |             |      |             |             |      |      |      |      | xor rax, rax
Total Num Of Uops: 48