IMUL (M32) - Port Usage

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	41 0f 7e c0          	movd   r8d,mm0
  1e:	41 0f 7e c1          	movd   r9d,mm0
  22:	41 0f 7e c2          	movd   r10d,mm0
  26:	41 f7 2e             	imul   DWORD PTR [r14]

Init:
```
PXOR MM0, MM0
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.06
- Reference cycles: 10.09
- UOPS_PORT_0: 10.01

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	41 f7 2e             	imul   DWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.09
- Reference cycles: 11.22
- UOPS_PORT_1: 10.99

⇨ One μop that can only use port '1'

With blocking instructions for port '5':

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	41 f7 2e             	imul   DWORD PTR [r14]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.06
- Reference cycles: 10.2
- UOPS_PORT_5: 9.99

With blocking instructions for ports {'0', '1'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	45 8d 06             	lea    r8d,[r14]
  18:	45 8d 0e             	lea    r9d,[r14]
  1b:	45 8d 16             	lea    r10d,[r14]
  1e:	45 8d 1e             	lea    r11d,[r14]
  21:	45 8d 26             	lea    r12d,[r14]
  24:	41 8d 1e             	lea    ebx,[r14]
  27:	41 8d 0e             	lea    ecx,[r14]
  2a:	45 8d 06             	lea    r8d,[r14]
  2d:	45 8d 0e             	lea    r9d,[r14]
  30:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 9.19
- Reference cycles: 9.23
- UOPS_PORT_1: 8.02
- UOPS_PORT_0: 8.98

With blocking instructions for ports {'0', '5'}:

Code:

   0:	66 41 c1 f8 00       	sar    r8w,0x0
   5:	66 41 c1 f9 00       	sar    r9w,0x0
   a:	66 41 c1 fa 00       	sar    r10w,0x0
   f:	66 41 c1 fb 00       	sar    r11w,0x0
  14:	66 41 c1 fc 00       	sar    r12w,0x0
  19:	66 c1 fb 00          	sar    bx,0x0
  1d:	66 c1 f9 00          	sar    cx,0x0
  21:	66 41 c1 f8 00       	sar    r8w,0x0
  26:	66 41 c1 f9 00       	sar    r9w,0x0
  2b:	66 41 c1 fa 00       	sar    r10w,0x0
  30:	66 41 c1 fb 00       	sar    r11w,0x0
  35:	66 41 c1 fc 00       	sar    r12w,0x0
  3a:	66 c1 fb 00          	sar    bx,0x0
  3e:	66 c1 f9 00          	sar    cx,0x0
  42:	66 41 c1 f8 00       	sar    r8w,0x0
  47:	66 41 c1 f9 00       	sar    r9w,0x0
  4c:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.6
- Reference cycles: 8.68
- UOPS_PORT_5: 8.5
- UOPS_PORT_0: 8.52

⇨ One μop that can only use ports {'0', '5'}

With blocking instructions for ports {'1', '5'}:

Code:

   0:	0f 38 1c c1          	pabsb  mm0,mm1
   4:	0f 38 1c d1          	pabsb  mm2,mm1
   8:	0f 38 1c d9          	pabsb  mm3,mm1
   c:	0f 38 1c e1          	pabsb  mm4,mm1
  10:	0f 38 1c e9          	pabsb  mm5,mm1
  14:	0f 38 1c f1          	pabsb  mm6,mm1
  18:	0f 38 1c f9          	pabsb  mm7,mm1
  1c:	0f 38 1c c1          	pabsb  mm0,mm1
  20:	0f 38 1c d1          	pabsb  mm2,mm1
  24:	0f 38 1c d9          	pabsb  mm3,mm1
  28:	0f 38 1c e1          	pabsb  mm4,mm1
  2c:	0f 38 1c e9          	pabsb  mm5,mm1
  30:	0f 38 1c f1          	pabsb  mm6,mm1
  34:	0f 38 1c f9          	pabsb  mm7,mm1
  38:	0f 38 1c c1          	pabsb  mm0,mm1
  3c:	0f 38 1c d1          	pabsb  mm2,mm1
  40:	41 f7 2e             	imul   DWORD PTR [r14]

Init:
```
VZEROALL;
PXOR MM1, MM1
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.66
- Reference cycles: 8.32
- UOPS_PORT_5: 8.48
- UOPS_PORT_1: 8.5

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	41 f7 2e             	imul   DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 9.47
- Reference cycles: 9.6
- UOPS_PORT_2: 8.48
- UOPS_PORT_3: 8.48

⇨ One μop that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	41 b0 00             	mov    r8b,0x0
   3:	41 b1 00             	mov    r9b,0x0
   6:	41 b2 00             	mov    r10b,0x0
   9:	41 b3 00             	mov    r11b,0x0
   c:	41 b4 00             	mov    r12b,0x0
   f:	b3 00                	mov    bl,0x0
  11:	b1 00                	mov    cl,0x0
  13:	41 b0 00             	mov    r8b,0x0
  16:	41 b1 00             	mov    r9b,0x0
  19:	41 b2 00             	mov    r10b,0x0
  1c:	41 b3 00             	mov    r11b,0x0
  1f:	41 b4 00             	mov    r12b,0x0
  22:	b3 00                	mov    bl,0x0
  24:	b1 00                	mov    cl,0x0
  26:	41 b0 00             	mov    r8b,0x0
  29:	41 b1 00             	mov    r9b,0x0
  2c:	41 b2 00             	mov    r10b,0x0
  2f:	41 b3 00             	mov    r11b,0x0
  32:	41 b4 00             	mov    r12b,0x0
  35:	b3 00                	mov    bl,0x0
  37:	b1 00                	mov    cl,0x0
  39:	41 b0 00             	mov    r8b,0x0
  3c:	41 b1 00             	mov    r9b,0x0
  3f:	41 b2 00             	mov    r10b,0x0
  42:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 9.83
- Reference cycles: 9.81
- UOPS_PORT_5: 9.07
- UOPS_PORT_1: 8.63
- UOPS_PORT_0: 9.29

⇨ One μop that can only use ports {'0', '1', '5'}

With an indexed addressing mode

With blocking instructions for port '0':

Code:

   0:	41 0f 7e c0          	movd   r8d,mm0
   4:	41 0f 7e c1          	movd   r9d,mm0
   8:	41 0f 7e c2          	movd   r10d,mm0
   c:	41 0f 7e c3          	movd   r11d,mm0
  10:	41 0f 7e c4          	movd   r12d,mm0
  14:	0f 7e c3             	movd   ebx,mm0
  17:	0f 7e c1             	movd   ecx,mm0
  1a:	41 0f 7e c0          	movd   r8d,mm0
  1e:	41 0f 7e c1          	movd   r9d,mm0
  22:	41 0f 7e c2          	movd   r10d,mm0
  26:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
PXOR MM0, MM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.06
- Reference cycles: 10.09
- UOPS_PORT_0: 10.01

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.06
- Reference cycles: 11.16
- UOPS_PORT_1: 10.99

⇨ One μop that can only use port '1'

With blocking instructions for port '5':

Code:

   0:	66 0f 55 c1          	andnpd xmm0,xmm1
   4:	66 0f 55 d1          	andnpd xmm2,xmm1
   8:	66 0f 55 d9          	andnpd xmm3,xmm1
   c:	66 0f 55 e1          	andnpd xmm4,xmm1
  10:	66 0f 55 e9          	andnpd xmm5,xmm1
  14:	66 0f 55 f1          	andnpd xmm6,xmm1
  18:	66 0f 55 f9          	andnpd xmm7,xmm1
  1c:	66 44 0f 55 c1       	andnpd xmm8,xmm1
  21:	66 44 0f 55 c9       	andnpd xmm9,xmm1
  26:	66 44 0f 55 d1       	andnpd xmm10,xmm1
  2b:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.06
- Reference cycles: 10.09
- UOPS_PORT_5: 10.0

With blocking instructions for ports {'0', '1'}:

Code:

   0:	45 8d 06             	lea    r8d,[r14]
   3:	45 8d 0e             	lea    r9d,[r14]
   6:	45 8d 16             	lea    r10d,[r14]
   9:	45 8d 1e             	lea    r11d,[r14]
   c:	45 8d 26             	lea    r12d,[r14]
   f:	41 8d 1e             	lea    ebx,[r14]
  12:	41 8d 0e             	lea    ecx,[r14]
  15:	45 8d 06             	lea    r8d,[r14]
  18:	45 8d 0e             	lea    r9d,[r14]
  1b:	45 8d 16             	lea    r10d,[r14]
  1e:	45 8d 1e             	lea    r11d,[r14]
  21:	45 8d 26             	lea    r12d,[r14]
  24:	41 8d 1e             	lea    ebx,[r14]
  27:	41 8d 0e             	lea    ecx,[r14]
  2a:	45 8d 06             	lea    r8d,[r14]
  2d:	45 8d 0e             	lea    r9d,[r14]
  30:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 9.18
- Reference cycles: 9.23
- UOPS_PORT_1: 8.02
- UOPS_PORT_0: 8.98

With blocking instructions for ports {'0', '5'}:

Code:

   0:	66 41 c1 f8 00       	sar    r8w,0x0
   5:	66 41 c1 f9 00       	sar    r9w,0x0
   a:	66 41 c1 fa 00       	sar    r10w,0x0
   f:	66 41 c1 fb 00       	sar    r11w,0x0
  14:	66 41 c1 fc 00       	sar    r12w,0x0
  19:	66 c1 fb 00          	sar    bx,0x0
  1d:	66 c1 f9 00          	sar    cx,0x0
  21:	66 41 c1 f8 00       	sar    r8w,0x0
  26:	66 41 c1 f9 00       	sar    r9w,0x0
  2b:	66 41 c1 fa 00       	sar    r10w,0x0
  30:	66 41 c1 fb 00       	sar    r11w,0x0
  35:	66 41 c1 fc 00       	sar    r12w,0x0
  3a:	66 c1 fb 00          	sar    bx,0x0
  3e:	66 c1 f9 00          	sar    cx,0x0
  42:	66 41 c1 f8 00       	sar    r8w,0x0
  47:	66 41 c1 f9 00       	sar    r9w,0x0
  4c:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.58
- Reference cycles: 8.68
- UOPS_PORT_5: 8.48
- UOPS_PORT_0: 8.53

⇨ One μop that can only use ports {'0', '5'}

With blocking instructions for ports {'1', '5'}:

Code:

   0:	0f 38 1c c1          	pabsb  mm0,mm1
   4:	0f 38 1c d1          	pabsb  mm2,mm1
   8:	0f 38 1c d9          	pabsb  mm3,mm1
   c:	0f 38 1c e1          	pabsb  mm4,mm1
  10:	0f 38 1c e9          	pabsb  mm5,mm1
  14:	0f 38 1c f1          	pabsb  mm6,mm1
  18:	0f 38 1c f9          	pabsb  mm7,mm1
  1c:	0f 38 1c c1          	pabsb  mm0,mm1
  20:	0f 38 1c d1          	pabsb  mm2,mm1
  24:	0f 38 1c d9          	pabsb  mm3,mm1
  28:	0f 38 1c e1          	pabsb  mm4,mm1
  2c:	0f 38 1c e9          	pabsb  mm5,mm1
  30:	0f 38 1c f1          	pabsb  mm6,mm1
  34:	0f 38 1c f9          	pabsb  mm7,mm1
  38:	0f 38 1c c1          	pabsb  mm0,mm1
  3c:	0f 38 1c d1          	pabsb  mm2,mm1
  40:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
PXOR MM1, MM1;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.66
- Reference cycles: 8.5
- UOPS_PORT_5: 8.47
- UOPS_PORT_1: 8.5

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 9.48
- Reference cycles: 9.78
- UOPS_PORT_2: 8.48
- UOPS_PORT_3: 8.48

⇨ One μop that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	41 b0 00             	mov    r8b,0x0
   3:	41 b1 00             	mov    r9b,0x0
   6:	41 b2 00             	mov    r10b,0x0
   9:	41 b3 00             	mov    r11b,0x0
   c:	41 b4 00             	mov    r12b,0x0
   f:	b3 00                	mov    bl,0x0
  11:	b1 00                	mov    cl,0x0
  13:	41 b0 00             	mov    r8b,0x0
  16:	41 b1 00             	mov    r9b,0x0
  19:	41 b2 00             	mov    r10b,0x0
  1c:	41 b3 00             	mov    r11b,0x0
  1f:	41 b4 00             	mov    r12b,0x0
  22:	b3 00                	mov    bl,0x0
  24:	b1 00                	mov    cl,0x0
  26:	41 b0 00             	mov    r8b,0x0
  29:	41 b1 00             	mov    r9b,0x0
  2c:	41 b2 00             	mov    r10b,0x0
  2f:	41 b3 00             	mov    r11b,0x0
  32:	41 b4 00             	mov    r12b,0x0
  35:	b3 00                	mov    bl,0x0
  37:	b1 00                	mov    cl,0x0
  39:	41 b0 00             	mov    r8b,0x0
  3c:	41 b1 00             	mov    r9b,0x0
  3f:	41 b2 00             	mov    r10b,0x0
  42:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 9.88
- Reference cycles: 9.95
- UOPS_PORT_5: 9.05
- UOPS_PORT_1: 8.63
- UOPS_PORT_0: 9.32

⇨ One μop that can only use ports {'0', '1', '5'}