IMUL (M32)

With unroll_count=500 and no inner loop

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 3.07
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 2.99
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.5
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.03
- Reference cycles: 3.1
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 3.95
- UOPS_MS: 0.07
- UOPS_PORT_0: 0.61
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.54
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.86
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	90                   	nop
   4:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.01
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 4.94
- UOPS_MS: 0.07
- UOPS_PORT_0: 0.56
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.57
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.88
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	90                   	nop
   4:	90                   	nop
   5:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.52
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.48
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 1.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	90                   	nop
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.0
- Reference cycles: 2.91
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 7.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.56
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.57
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.88
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.01
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.26
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.55
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.66
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.89
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.09

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.0
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.55
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.66
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.89
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.01
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 3.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.54
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.56
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.91
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.01
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.54
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.56
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.91
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 0.7
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.52
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.54
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.94
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 4.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.54
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.63
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.94
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.55
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.65
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.9
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 4.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.53
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.55
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.94
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 1.01
- Reference cycles: 0.76
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.56
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.57
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.88
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 16.0
- Reference cycles: 12.0
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.0
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 4.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 16.02
- Reference cycles: 12.05
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.46
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.21
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.72
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.57
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.15

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	41 f7 2e             	imul   DWORD PTR [r14]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 16.02
- Reference cycles: 12.04
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.21
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.72
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.57
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 16.02
- Reference cycles: 12.05
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 12.04
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.16
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.24
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.65
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	41 f7 2e             	imul   DWORD PTR [r14]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 16.02
- Reference cycles: 12.05
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.11
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.16
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.24
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.65
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.09
- Reference cycles: 2.96
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 15.87
- UOPS_MS: 0.19
- UOPS_PORT_0: 2.11
- UOPS_PORT_1: 4.01
- UOPS_PORT_6: 2.17
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.72
- UOPS_PORT_5B>=2: 0.01
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.97

With loop_count=1000 and unroll_count=2

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 4.01
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 16.5
- UOPS_MITE: 1.11
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.25
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.67
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.73
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.27

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	41 f7 2e             	imul   DWORD PTR [r14]
  11:	48 31 c0             	xor    rax,rax
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
  23:	48 31 c0             	xor    rax,rax
  26:	40                   	rex
  27:	40                   	rex
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  35:	48 31 c0             	xor    rax,rax
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	40                   	rex
  3d:	40                   	rex
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 4.01
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 16.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.26
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.67
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.58
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 8.1
- Core cycles: 4.01
- Reference cycles: 3.02
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 16.05
- UOPS_MITE: 16.04
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.11
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.19
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.75
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	41 f7 2e             	imul   DWORD PTR [r14]
  11:	48 31 c0             	xor    rax,rax
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
  23:	48 31 c0             	xor    rax,rax
  26:	40                   	rex
  27:	40                   	rex
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  35:	48 31 c0             	xor    rax,rax
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	40                   	rex
  3d:	40                   	rex
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]

Show nanoBench command
Results:
- Instructions retired: 8.1
- Core cycles: 4.01
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 16.05
- UOPS_MITE: 0.24
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.24
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.27
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.53
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 32.0
- Reference cycles: 24.0
- UOPS_EXECUTED.THREAD: 32.01
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 24.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 4.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 8.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.01

With loop_count=1000 and unroll_count=1

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 32.03
- Reference cycles: 24.1
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.91
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.41
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 5.44
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.14
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.34

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	41 f7 2e             	imul   DWORD PTR [r14]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	40                   	rex
  28:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	40                   	rex
  3a:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 32.04
- Reference cycles: 24.1
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.42
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 5.45
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.13
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 32.04
- Reference cycles: 24.1
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 24.08
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.32
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 4.48
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.3
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.99

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	41 f7 2e             	imul   DWORD PTR [r14]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	40                   	rex
  28:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	40                   	rex
  3a:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 32.04
- Reference cycles: 24.08
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.22
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.32
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 4.48
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.3
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.01
- Reference cycles: 6.24
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 32.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.19
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 4.32
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.57
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.02
- Reference cycles: 6.06
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.01
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.52
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 5.35
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.14
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	41 f7 2e             	imul   DWORD PTR [r14]
  11:	48 31 c0             	xor    rax,rax
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
  23:	48 31 c0             	xor    rax,rax
  26:	40                   	rex
  27:	40                   	rex
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  35:	48 31 c0             	xor    rax,rax
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	40                   	rex
  3d:	40                   	rex
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  47:	48 31 c0             	xor    rax,rax
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	40                   	rex
  4d:	40                   	rex
  4e:	40                   	rex
  4f:	40                   	rex
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	40                   	rex
  55:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  59:	48 31 c0             	xor    rax,rax
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	40                   	rex
  5f:	40                   	rex
  60:	40                   	rex
  61:	40                   	rex
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	40                   	rex
  67:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  6b:	48 31 c0             	xor    rax,rax
  6e:	40                   	rex
  6f:	40                   	rex
  70:	40                   	rex
  71:	40                   	rex
  72:	40                   	rex
  73:	40                   	rex
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	40                   	rex
  79:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  7d:	48 31 c0             	xor    rax,rax
  80:	40                   	rex
  81:	40                   	rex
  82:	40                   	rex
  83:	40                   	rex
  84:	40                   	rex
  85:	40                   	rex
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	40                   	rex
  8b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.02
- Reference cycles: 6.05
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.5
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 5.34
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.14
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.01
- Reference cycles: 5.98
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.29
- UOPS_MS: 0.03
- UOPS_PORT_0: 4.49
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 4.54
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.06
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	41 f7 2e             	imul   DWORD PTR [r14]
  11:	48 31 c0             	xor    rax,rax
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
  23:	48 31 c0             	xor    rax,rax
  26:	40                   	rex
  27:	40                   	rex
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  35:	48 31 c0             	xor    rax,rax
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	40                   	rex
  3d:	40                   	rex
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  47:	48 31 c0             	xor    rax,rax
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	40                   	rex
  4d:	40                   	rex
  4e:	40                   	rex
  4f:	40                   	rex
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	40                   	rex
  55:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  59:	48 31 c0             	xor    rax,rax
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	40                   	rex
  5f:	40                   	rex
  60:	40                   	rex
  61:	40                   	rex
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	40                   	rex
  67:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  6b:	48 31 c0             	xor    rax,rax
  6e:	40                   	rex
  6f:	40                   	rex
  70:	40                   	rex
  71:	40                   	rex
  72:	40                   	rex
  73:	40                   	rex
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	40                   	rex
  79:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  7d:	48 31 c0             	xor    rax,rax
  80:	40                   	rex
  81:	40                   	rex
  82:	40                   	rex
  83:	40                   	rex
  84:	40                   	rex
  85:	40                   	rex
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	40                   	rex
  8b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.01
- Reference cycles: 6.05
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.3
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.5
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 4.54
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.06
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  1f:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  23:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  27:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  2b:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  2f:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  33:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  37:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  3b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 64.0
- Reference cycles: 48.0
- UOPS_EXECUTED.THREAD: 63.99
- RETIRE_SLOTS: 48.0
- UOPS_MITE: 47.7
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 8.0
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 16.0
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 15.99

With loop_count=1000 and unroll_count=1

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  1f:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  23:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  27:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  2b:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  2f:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  33:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  37:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  3b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 64.1
- Reference cycles: 48.26
- UOPS_EXECUTED.THREAD: 65.0
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 49.09
- UOPS_MS: 0.04
- UOPS_PORT_0: 8.81
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 9.92
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.28
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.03

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	41 f7 2e             	imul   DWORD PTR [r14]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	40                   	rex
  28:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	40                   	rex
  3a:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	40                   	rex
  55:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	40                   	rex
  67:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	40                   	rex
  6f:	40                   	rex
  70:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	40                   	rex
  79:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	40                   	rex
  81:	40                   	rex
  82:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	40                   	rex
  8b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 64.07
- Reference cycles: 48.24
- UOPS_EXECUTED.THREAD: 65.0
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.04
- UOPS_PORT_0: 8.71
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 9.78
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.4
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   7:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
   b:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
   f:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  13:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  17:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  1b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  1f:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  23:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  27:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  2b:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  2f:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  33:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  37:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  3b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 64.06
- Reference cycles: 48.19
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 48.08
- UOPS_MS: 0.04
- UOPS_PORT_0: 8.6
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 8.84
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.67
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 15.99

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	40                   	rex
   5:	41 f7 2e             	imul   DWORD PTR [r14]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	40                   	rex
  16:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	40                   	rex
  28:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	40                   	rex
  3a:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	40                   	rex
  55:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	40                   	rex
  67:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	40                   	rex
  6f:	40                   	rex
  70:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	40                   	rex
  79:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	40                   	rex
  81:	40                   	rex
  82:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	40                   	rex
  8b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 64.06
- Reference cycles: 48.18
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 0.47
- UOPS_MS: 0.04
- UOPS_PORT_0: 8.6
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 8.84
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.67
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  37:	48 31 c0             	xor    rax,rax
  3a:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  3e:	48 31 c0             	xor    rax,rax
  41:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  45:	48 31 c0             	xor    rax,rax
  48:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  4c:	48 31 c0             	xor    rax,rax
  4f:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  53:	48 31 c0             	xor    rax,rax
  56:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  5a:	48 31 c0             	xor    rax,rax
  5d:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  61:	48 31 c0             	xor    rax,rax
  64:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  68:	48 31 c0             	xor    rax,rax
  6b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 32.0
- Core cycles: 16.0
- Reference cycles: 12.0
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 64.0
- UOPS_MITE: 64.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.39
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 8.61
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 15.04
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  37:	48 31 c0             	xor    rax,rax
  3a:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  3e:	48 31 c0             	xor    rax,rax
  41:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  45:	48 31 c0             	xor    rax,rax
  48:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  4c:	48 31 c0             	xor    rax,rax
  4f:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  53:	48 31 c0             	xor    rax,rax
  56:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  5a:	48 31 c0             	xor    rax,rax
  5d:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  61:	48 31 c0             	xor    rax,rax
  64:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  68:	48 31 c0             	xor    rax,rax
  6b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 34.0
- Core cycles: 16.02
- Reference cycles: 12.06
- UOPS_EXECUTED.THREAD: 65.0
- RETIRE_SLOTS: 65.0
- UOPS_MITE: 0.26
- UOPS_MS: 0.04
- UOPS_PORT_0: 8.75
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 9.72
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.48
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	41 f7 2e             	imul   DWORD PTR [r14]
  11:	48 31 c0             	xor    rax,rax
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
  23:	48 31 c0             	xor    rax,rax
  26:	40                   	rex
  27:	40                   	rex
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  35:	48 31 c0             	xor    rax,rax
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	40                   	rex
  3d:	40                   	rex
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  47:	48 31 c0             	xor    rax,rax
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	40                   	rex
  4d:	40                   	rex
  4e:	40                   	rex
  4f:	40                   	rex
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	40                   	rex
  55:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  59:	48 31 c0             	xor    rax,rax
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	40                   	rex
  5f:	40                   	rex
  60:	40                   	rex
  61:	40                   	rex
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	40                   	rex
  67:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  6b:	48 31 c0             	xor    rax,rax
  6e:	40                   	rex
  6f:	40                   	rex
  70:	40                   	rex
  71:	40                   	rex
  72:	40                   	rex
  73:	40                   	rex
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	40                   	rex
  79:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  7d:	48 31 c0             	xor    rax,rax
  80:	40                   	rex
  81:	40                   	rex
  82:	40                   	rex
  83:	40                   	rex
  84:	40                   	rex
  85:	40                   	rex
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	40                   	rex
  8b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  8f:	48 31 c0             	xor    rax,rax
  92:	40                   	rex
  93:	40                   	rex
  94:	40                   	rex
  95:	40                   	rex
  96:	40                   	rex
  97:	40                   	rex
  98:	40                   	rex
  99:	40                   	rex
  9a:	40                   	rex
  9b:	40                   	rex
  9c:	40                   	rex
  9d:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  a1:	48 31 c0             	xor    rax,rax
  a4:	40                   	rex
  a5:	40                   	rex
  a6:	40                   	rex
  a7:	40                   	rex
  a8:	40                   	rex
  a9:	40                   	rex
  aa:	40                   	rex
  ab:	40                   	rex
  ac:	40                   	rex
  ad:	40                   	rex
  ae:	40                   	rex
  af:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  b3:	48 31 c0             	xor    rax,rax
  b6:	40                   	rex
  b7:	40                   	rex
  b8:	40                   	rex
  b9:	40                   	rex
  ba:	40                   	rex
  bb:	40                   	rex
  bc:	40                   	rex
  bd:	40                   	rex
  be:	40                   	rex
  bf:	40                   	rex
  c0:	40                   	rex
  c1:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  c5:	48 31 c0             	xor    rax,rax
  c8:	40                   	rex
  c9:	40                   	rex
  ca:	40                   	rex
  cb:	40                   	rex
  cc:	40                   	rex
  cd:	40                   	rex
  ce:	40                   	rex
  cf:	40                   	rex
  d0:	40                   	rex
  d1:	40                   	rex
  d2:	40                   	rex
  d3:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  d7:	48 31 c0             	xor    rax,rax
  da:	40                   	rex
  db:	40                   	rex
  dc:	40                   	rex
  dd:	40                   	rex
  de:	40                   	rex
  df:	40                   	rex
  e0:	40                   	rex
  e1:	40                   	rex
  e2:	40                   	rex
  e3:	40                   	rex
  e4:	40                   	rex
  e5:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  e9:	48 31 c0             	xor    rax,rax
  ec:	40                   	rex
  ed:	40                   	rex
  ee:	40                   	rex
  ef:	40                   	rex
  f0:	40                   	rex
  f1:	40                   	rex
  f2:	40                   	rex
  f3:	40                   	rex
  f4:	40                   	rex
  f5:	40                   	rex
  f6:	40                   	rex
  f7:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  fb:	48 31 c0             	xor    rax,rax
  fe:	40                   	rex
  ff:	40                   	rex
 100:	40                   	rex
 101:	40                   	rex
 102:	40                   	rex
 103:	40                   	rex
 104:	40                   	rex
 105:	40                   	rex
 106:	40                   	rex
 107:	40                   	rex
 108:	40                   	rex
 109:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
 10d:	48 31 c0             	xor    rax,rax
 110:	40                   	rex
 111:	40                   	rex
 112:	40                   	rex
 113:	40                   	rex
 114:	40                   	rex
 115:	40                   	rex
 116:	40                   	rex
 117:	40                   	rex
 118:	40                   	rex
 119:	40                   	rex
 11a:	40                   	rex
 11b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 34.0
- Core cycles: 16.02
- Reference cycles: 12.05
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 65.01
- UOPS_MITE: 0.04
- UOPS_MS: 0.01
- UOPS_PORT_0: 8.75
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 9.72
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.33
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	41 f7 2e             	imul   DWORD PTR [r14]
   6:	48 31 c0             	xor    rax,rax
   9:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
   d:	48 31 c0             	xor    rax,rax
  10:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  14:	48 31 c0             	xor    rax,rax
  17:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  1b:	48 31 c0             	xor    rax,rax
  1e:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  22:	48 31 c0             	xor    rax,rax
  25:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  29:	48 31 c0             	xor    rax,rax
  2c:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  30:	48 31 c0             	xor    rax,rax
  33:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  37:	48 31 c0             	xor    rax,rax
  3a:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  3e:	48 31 c0             	xor    rax,rax
  41:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  45:	48 31 c0             	xor    rax,rax
  48:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  4c:	48 31 c0             	xor    rax,rax
  4f:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  53:	48 31 c0             	xor    rax,rax
  56:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  5a:	48 31 c0             	xor    rax,rax
  5d:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  61:	48 31 c0             	xor    rax,rax
  64:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
  68:	48 31 c0             	xor    rax,rax
  6b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 32.2
- Core cycles: 16.02
- Reference cycles: 12.05
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 64.1
- UOPS_MITE: 0.63
- UOPS_MS: 0.04
- UOPS_PORT_0: 9.02
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 8.95
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.13
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	40                   	rex
   e:	41 f7 2e             	imul   DWORD PTR [r14]
  11:	48 31 c0             	xor    rax,rax
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	40                   	rex
  1f:	41 f7 6e 04          	imul   DWORD PTR [r14+0x4]
  23:	48 31 c0             	xor    rax,rax
  26:	40                   	rex
  27:	40                   	rex
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	40                   	rex
  31:	41 f7 6e 08          	imul   DWORD PTR [r14+0x8]
  35:	48 31 c0             	xor    rax,rax
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	40                   	rex
  3d:	40                   	rex
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	40                   	rex
  43:	41 f7 6e 0c          	imul   DWORD PTR [r14+0xc]
  47:	48 31 c0             	xor    rax,rax
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	40                   	rex
  4d:	40                   	rex
  4e:	40                   	rex
  4f:	40                   	rex
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	40                   	rex
  55:	41 f7 6e 10          	imul   DWORD PTR [r14+0x10]
  59:	48 31 c0             	xor    rax,rax
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	40                   	rex
  5f:	40                   	rex
  60:	40                   	rex
  61:	40                   	rex
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	40                   	rex
  67:	41 f7 6e 14          	imul   DWORD PTR [r14+0x14]
  6b:	48 31 c0             	xor    rax,rax
  6e:	40                   	rex
  6f:	40                   	rex
  70:	40                   	rex
  71:	40                   	rex
  72:	40                   	rex
  73:	40                   	rex
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	40                   	rex
  79:	41 f7 6e 18          	imul   DWORD PTR [r14+0x18]
  7d:	48 31 c0             	xor    rax,rax
  80:	40                   	rex
  81:	40                   	rex
  82:	40                   	rex
  83:	40                   	rex
  84:	40                   	rex
  85:	40                   	rex
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	40                   	rex
  8b:	41 f7 6e 1c          	imul   DWORD PTR [r14+0x1c]
  8f:	48 31 c0             	xor    rax,rax
  92:	40                   	rex
  93:	40                   	rex
  94:	40                   	rex
  95:	40                   	rex
  96:	40                   	rex
  97:	40                   	rex
  98:	40                   	rex
  99:	40                   	rex
  9a:	40                   	rex
  9b:	40                   	rex
  9c:	40                   	rex
  9d:	41 f7 6e 20          	imul   DWORD PTR [r14+0x20]
  a1:	48 31 c0             	xor    rax,rax
  a4:	40                   	rex
  a5:	40                   	rex
  a6:	40                   	rex
  a7:	40                   	rex
  a8:	40                   	rex
  a9:	40                   	rex
  aa:	40                   	rex
  ab:	40                   	rex
  ac:	40                   	rex
  ad:	40                   	rex
  ae:	40                   	rex
  af:	41 f7 6e 24          	imul   DWORD PTR [r14+0x24]
  b3:	48 31 c0             	xor    rax,rax
  b6:	40                   	rex
  b7:	40                   	rex
  b8:	40                   	rex
  b9:	40                   	rex
  ba:	40                   	rex
  bb:	40                   	rex
  bc:	40                   	rex
  bd:	40                   	rex
  be:	40                   	rex
  bf:	40                   	rex
  c0:	40                   	rex
  c1:	41 f7 6e 28          	imul   DWORD PTR [r14+0x28]
  c5:	48 31 c0             	xor    rax,rax
  c8:	40                   	rex
  c9:	40                   	rex
  ca:	40                   	rex
  cb:	40                   	rex
  cc:	40                   	rex
  cd:	40                   	rex
  ce:	40                   	rex
  cf:	40                   	rex
  d0:	40                   	rex
  d1:	40                   	rex
  d2:	40                   	rex
  d3:	41 f7 6e 2c          	imul   DWORD PTR [r14+0x2c]
  d7:	48 31 c0             	xor    rax,rax
  da:	40                   	rex
  db:	40                   	rex
  dc:	40                   	rex
  dd:	40                   	rex
  de:	40                   	rex
  df:	40                   	rex
  e0:	40                   	rex
  e1:	40                   	rex
  e2:	40                   	rex
  e3:	40                   	rex
  e4:	40                   	rex
  e5:	41 f7 6e 30          	imul   DWORD PTR [r14+0x30]
  e9:	48 31 c0             	xor    rax,rax
  ec:	40                   	rex
  ed:	40                   	rex
  ee:	40                   	rex
  ef:	40                   	rex
  f0:	40                   	rex
  f1:	40                   	rex
  f2:	40                   	rex
  f3:	40                   	rex
  f4:	40                   	rex
  f5:	40                   	rex
  f6:	40                   	rex
  f7:	41 f7 6e 34          	imul   DWORD PTR [r14+0x34]
  fb:	48 31 c0             	xor    rax,rax
  fe:	40                   	rex
  ff:	40                   	rex
 100:	40                   	rex
 101:	40                   	rex
 102:	40                   	rex
 103:	40                   	rex
 104:	40                   	rex
 105:	40                   	rex
 106:	40                   	rex
 107:	40                   	rex
 108:	40                   	rex
 109:	41 f7 6e 38          	imul   DWORD PTR [r14+0x38]
 10d:	48 31 c0             	xor    rax,rax
 110:	40                   	rex
 111:	40                   	rex
 112:	40                   	rex
 113:	40                   	rex
 114:	40                   	rex
 115:	40                   	rex
 116:	40                   	rex
 117:	40                   	rex
 118:	40                   	rex
 119:	40                   	rex
 11a:	40                   	rex
 11b:	41 f7 6e 3c          	imul   DWORD PTR [r14+0x3c]

Show nanoBench command
Results:
- Instructions retired: 32.2
- Core cycles: 16.02
- Reference cycles: 12.02
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 64.1
- UOPS_MITE: 0.63
- UOPS_MS: 0.03
- UOPS_PORT_0: 9.01
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 8.96
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.13
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.27

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.02
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 2.98
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.54
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.54
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.92
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.07
- Reference cycles: 3.07
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 3.95
- UOPS_MS: 0.07
- UOPS_PORT_0: 0.55
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.56
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.89
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	90                   	nop
   5:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.02
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 3.99
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 4.94
- UOPS_MS: 0.07
- UOPS_PORT_0: 0.57
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.58
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.85
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.99

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 2.94
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 7.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.56
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.56
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.88
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 4 NOPs

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.04
- Reference cycles: 3.07
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 6.97
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.54
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.55
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.91
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.03
- Reference cycles: 3.03
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 0.41
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.54
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.64
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.91
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 4.03
- Reference cycles: 3.04
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 4.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.54
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.64
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.92
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.01
- Reference cycles: 3.01
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 3.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.54
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.55
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.92
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 4.01
- Reference cycles: 3.02
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 4.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.54
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.55
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.92
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 0.83
- UOPS_EXECUTED.THREAD: 3.99
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.59
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.62
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.8
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 5.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.58
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.67
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.85
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.2
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 4.1
- RETIRE_SLOTS: 5.1
- UOPS_MITE: 0.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.58
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.67
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.86
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 5.01
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.57
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.6
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.84
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.02
- Core cycles: 1.0
- Reference cycles: 0.75
- UOPS_EXECUTED.THREAD: 4.01
- RETIRE_SLOTS: 5.01
- UOPS_MITE: 0.04
- UOPS_MS: 0.0
- UOPS_PORT_0: 0.57
- UOPS_PORT_1: 1.0
- UOPS_PORT_6: 0.6
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 0.84
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 1.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.67

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 16.08
- Reference cycles: 12.0
- UOPS_EXECUTED.THREAD: 15.99
- RETIRE_SLOTS: 16.0
- UOPS_MITE: 11.89
- UOPS_MS: 0.18
- UOPS_PORT_0: 2.16
- UOPS_PORT_1: 4.01
- UOPS_PORT_6: 2.17
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.68
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.97

With loop_count=1000 and unroll_count=2

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 16.17
- Reference cycles: 12.16
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 16.5
- UOPS_MITE: 0.43
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.18
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.67
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.65
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.14

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 16.16
- Reference cycles: 12.15
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 16.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.18
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.67
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.65
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 16.04
- Reference cycles: 12.07
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 16.05
- UOPS_MITE: 12.03
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.15
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.21
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.67
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 3.99

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 16.04
- Reference cycles: 12.06
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 16.05
- UOPS_MITE: 0.1
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.16
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.23
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.67
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.03

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 4.0
- Reference cycles: 3.2
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 20.0
- UOPS_MITE: 15.85
- UOPS_MS: 0.0
- UOPS_PORT_0: 2.37
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.46
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.2
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 4.02
- Reference cycles: 3.02
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 20.5
- UOPS_MITE: 0.0
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.36
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.75
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.4
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
  11:	48 31 c0             	xor    rax,rax
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
  23:	48 31 c0             	xor    rax,rax
  26:	40                   	rex
  27:	40                   	rex
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  35:	48 31 c0             	xor    rax,rax
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	40                   	rex
  3d:	40                   	rex
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 4.02
- Reference cycles: 3.02
- UOPS_EXECUTED.THREAD: 16.5
- RETIRE_SLOTS: 20.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.37
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.74
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.42
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.1
- Core cycles: 4.01
- Reference cycles: 3.02
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 20.05
- UOPS_MITE: 0.15
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.3
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.41
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.35
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
  11:	48 31 c0             	xor    rax,rax
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
  23:	48 31 c0             	xor    rax,rax
  26:	40                   	rex
  27:	40                   	rex
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  35:	48 31 c0             	xor    rax,rax
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	40                   	rex
  3d:	40                   	rex
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.1
- Core cycles: 4.01
- Reference cycles: 3.02
- UOPS_EXECUTED.THREAD: 16.05
- RETIRE_SLOTS: 20.05
- UOPS_MITE: 0.22
- UOPS_MS: 0.02
- UOPS_PORT_0: 2.3
- UOPS_PORT_1: 4.0
- UOPS_PORT_6: 2.41
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 3.33
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 4.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 32.16
- Reference cycles: 24.0
- UOPS_EXECUTED.THREAD: 31.98
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 23.76
- UOPS_MS: 0.36
- UOPS_PORT_0: 4.32
- UOPS_PORT_1: 8.01
- UOPS_PORT_6: 4.33
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.35
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.93

With loop_count=1000 and unroll_count=1

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 32.33
- Reference cycles: 24.29
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.85
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.35
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 5.34
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.3
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.32

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 32.31
- Reference cycles: 24.3
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 33.0
- UOPS_MITE: 0.0
- UOPS_MS: 0.06
- UOPS_PORT_0: 4.35
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 5.34
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.3
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 32.09
- Reference cycles: 24.16
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 24.07
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.31
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 4.42
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.33
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 7.99

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 32.11
- Reference cycles: 24.16
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 32.1
- UOPS_MITE: 0.21
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.31
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 4.42
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 7.37
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 8.0
- Reference cycles: 6.4
- UOPS_EXECUTED.THREAD: 31.99
- RETIRE_SLOTS: 40.0
- UOPS_MITE: 31.71
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.73
- UOPS_PORT_1: 8.01
- UOPS_PORT_6: 4.92
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.35
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.03
- Reference cycles: 6.06
- UOPS_EXECUTED.THREAD: 33.01
- RETIRE_SLOTS: 41.0
- UOPS_MITE: 0.0
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.71
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 5.49
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.81
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
  11:	48 31 c0             	xor    rax,rax
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
  23:	48 31 c0             	xor    rax,rax
  26:	40                   	rex
  27:	40                   	rex
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  35:	48 31 c0             	xor    rax,rax
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	40                   	rex
  3d:	40                   	rex
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  47:	48 31 c0             	xor    rax,rax
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	40                   	rex
  4d:	40                   	rex
  4e:	40                   	rex
  4f:	40                   	rex
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  59:	48 31 c0             	xor    rax,rax
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	40                   	rex
  5f:	40                   	rex
  60:	40                   	rex
  61:	40                   	rex
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  6b:	48 31 c0             	xor    rax,rax
  6e:	40                   	rex
  6f:	40                   	rex
  70:	40                   	rex
  71:	40                   	rex
  72:	40                   	rex
  73:	40                   	rex
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  7d:	48 31 c0             	xor    rax,rax
  80:	40                   	rex
  81:	40                   	rex
  82:	40                   	rex
  83:	40                   	rex
  84:	40                   	rex
  85:	40                   	rex
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 8.03
- Reference cycles: 6.05
- UOPS_EXECUTED.THREAD: 33.0
- RETIRE_SLOTS: 41.0
- UOPS_MITE: 0.02
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.74
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 5.45
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.86
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.02
- Reference cycles: 6.03
- UOPS_EXECUTED.THREAD: 32.09
- RETIRE_SLOTS: 40.1
- UOPS_MITE: 0.29
- UOPS_MS: 0.03
- UOPS_PORT_0: 4.61
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 4.87
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.63
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
  11:	48 31 c0             	xor    rax,rax
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
  23:	48 31 c0             	xor    rax,rax
  26:	40                   	rex
  27:	40                   	rex
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  35:	48 31 c0             	xor    rax,rax
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	40                   	rex
  3d:	40                   	rex
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  47:	48 31 c0             	xor    rax,rax
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	40                   	rex
  4d:	40                   	rex
  4e:	40                   	rex
  4f:	40                   	rex
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  59:	48 31 c0             	xor    rax,rax
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	40                   	rex
  5f:	40                   	rex
  60:	40                   	rex
  61:	40                   	rex
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  6b:	48 31 c0             	xor    rax,rax
  6e:	40                   	rex
  6f:	40                   	rex
  70:	40                   	rex
  71:	40                   	rex
  72:	40                   	rex
  73:	40                   	rex
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  7d:	48 31 c0             	xor    rax,rax
  80:	40                   	rex
  81:	40                   	rex
  82:	40                   	rex
  83:	40                   	rex
  84:	40                   	rex
  85:	40                   	rex
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 8.02
- Reference cycles: 6.05
- UOPS_EXECUTED.THREAD: 32.1
- RETIRE_SLOTS: 40.1
- UOPS_MITE: 0.49
- UOPS_MS: 0.04
- UOPS_PORT_0: 4.59
- UOPS_PORT_1: 8.0
- UOPS_PORT_6: 4.85
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 6.71
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 8.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  27:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  2c:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  31:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  36:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  3b:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  40:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  45:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  4a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 64.16
- Reference cycles: 48.0
- UOPS_EXECUTED.THREAD: 63.98
- RETIRE_SLOTS: 64.0
- UOPS_MITE: 47.4
- UOPS_MS: 0.36
- UOPS_PORT_0: 8.63
- UOPS_PORT_1: 16.01
- UOPS_PORT_6: 8.64
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.73
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 15.93

With loop_count=1000 and unroll_count=1

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  27:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  2c:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  31:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  36:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  3b:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  40:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  45:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  4a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 64.4
- Reference cycles: 48.46
- UOPS_EXECUTED.THREAD: 65.0
- RETIRE_SLOTS: 65.0
- UOPS_MITE: 49.1
- UOPS_MS: 0.04
- UOPS_PORT_0: 8.65
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 9.65
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.69
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.03

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	40                   	rex
  4b:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	40                   	rex
  5d:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	40                   	rex
  6f:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	40                   	rex
  81:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 64.4
- Reference cycles: 48.46
- UOPS_EXECUTED.THREAD: 65.0
- RETIRE_SLOTS: 65.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.04
- UOPS_PORT_0: 8.64
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 9.67
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.69
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   9:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
   e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  13:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  18:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  1d:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  22:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  27:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  2c:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  31:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  36:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  3b:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  40:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  45:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  4a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 64.13
- Reference cycles: 48.26
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 64.1
- UOPS_MITE: 48.08
- UOPS_MS: 0.04
- UOPS_PORT_0: 8.62
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 8.72
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.59
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 15.99

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	40                   	rex
  4b:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	40                   	rex
  5d:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	40                   	rex
  6f:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	40                   	rex
  81:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 64.12
- Reference cycles: 48.22
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 64.1
- UOPS_MITE: 0.75
- UOPS_MS: 0.04
- UOPS_PORT_0: 8.62
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 8.74
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 14.74
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.27

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  3f:	48 31 c0             	xor    rax,rax
  42:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  47:	48 31 c0             	xor    rax,rax
  4a:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  4f:	48 31 c0             	xor    rax,rax
  52:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  57:	48 31 c0             	xor    rax,rax
  5a:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  5f:	48 31 c0             	xor    rax,rax
  62:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  67:	48 31 c0             	xor    rax,rax
  6a:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  6f:	48 31 c0             	xor    rax,rax
  72:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  77:	48 31 c0             	xor    rax,rax
  7a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 32.0
- Core cycles: 16.01
- Reference cycles: 12.0
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 80.0
- UOPS_MITE: 64.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 9.25
- UOPS_PORT_1: 16.01
- UOPS_PORT_6: 9.75
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 12.99
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  3f:	48 31 c0             	xor    rax,rax
  42:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  47:	48 31 c0             	xor    rax,rax
  4a:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  4f:	48 31 c0             	xor    rax,rax
  52:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  57:	48 31 c0             	xor    rax,rax
  5a:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  5f:	48 31 c0             	xor    rax,rax
  62:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  67:	48 31 c0             	xor    rax,rax
  6a:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  6f:	48 31 c0             	xor    rax,rax
  72:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  77:	48 31 c0             	xor    rax,rax
  7a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 34.0
- Core cycles: 16.03
- Reference cycles: 12.1
- UOPS_EXECUTED.THREAD: 65.0
- RETIRE_SLOTS: 81.0
- UOPS_MITE: 0.04
- UOPS_MS: 0.04
- UOPS_PORT_0: 9.32
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 10.26
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 13.48
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
  11:	48 31 c0             	xor    rax,rax
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
  23:	48 31 c0             	xor    rax,rax
  26:	40                   	rex
  27:	40                   	rex
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  35:	48 31 c0             	xor    rax,rax
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	40                   	rex
  3d:	40                   	rex
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  47:	48 31 c0             	xor    rax,rax
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	40                   	rex
  4d:	40                   	rex
  4e:	40                   	rex
  4f:	40                   	rex
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  59:	48 31 c0             	xor    rax,rax
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	40                   	rex
  5f:	40                   	rex
  60:	40                   	rex
  61:	40                   	rex
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  6b:	48 31 c0             	xor    rax,rax
  6e:	40                   	rex
  6f:	40                   	rex
  70:	40                   	rex
  71:	40                   	rex
  72:	40                   	rex
  73:	40                   	rex
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  7d:	48 31 c0             	xor    rax,rax
  80:	40                   	rex
  81:	40                   	rex
  82:	40                   	rex
  83:	40                   	rex
  84:	40                   	rex
  85:	40                   	rex
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  8f:	48 31 c0             	xor    rax,rax
  92:	40                   	rex
  93:	40                   	rex
  94:	40                   	rex
  95:	40                   	rex
  96:	40                   	rex
  97:	40                   	rex
  98:	40                   	rex
  99:	40                   	rex
  9a:	40                   	rex
  9b:	40                   	rex
  9c:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  a1:	48 31 c0             	xor    rax,rax
  a4:	40                   	rex
  a5:	40                   	rex
  a6:	40                   	rex
  a7:	40                   	rex
  a8:	40                   	rex
  a9:	40                   	rex
  aa:	40                   	rex
  ab:	40                   	rex
  ac:	40                   	rex
  ad:	40                   	rex
  ae:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  b3:	48 31 c0             	xor    rax,rax
  b6:	40                   	rex
  b7:	40                   	rex
  b8:	40                   	rex
  b9:	40                   	rex
  ba:	40                   	rex
  bb:	40                   	rex
  bc:	40                   	rex
  bd:	40                   	rex
  be:	40                   	rex
  bf:	40                   	rex
  c0:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  c5:	48 31 c0             	xor    rax,rax
  c8:	40                   	rex
  c9:	40                   	rex
  ca:	40                   	rex
  cb:	40                   	rex
  cc:	40                   	rex
  cd:	40                   	rex
  ce:	40                   	rex
  cf:	40                   	rex
  d0:	40                   	rex
  d1:	40                   	rex
  d2:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  d7:	48 31 c0             	xor    rax,rax
  da:	40                   	rex
  db:	40                   	rex
  dc:	40                   	rex
  dd:	40                   	rex
  de:	40                   	rex
  df:	40                   	rex
  e0:	40                   	rex
  e1:	40                   	rex
  e2:	40                   	rex
  e3:	40                   	rex
  e4:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  e9:	48 31 c0             	xor    rax,rax
  ec:	40                   	rex
  ed:	40                   	rex
  ee:	40                   	rex
  ef:	40                   	rex
  f0:	40                   	rex
  f1:	40                   	rex
  f2:	40                   	rex
  f3:	40                   	rex
  f4:	40                   	rex
  f5:	40                   	rex
  f6:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  fb:	48 31 c0             	xor    rax,rax
  fe:	40                   	rex
  ff:	40                   	rex
 100:	40                   	rex
 101:	40                   	rex
 102:	40                   	rex
 103:	40                   	rex
 104:	40                   	rex
 105:	40                   	rex
 106:	40                   	rex
 107:	40                   	rex
 108:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
 10d:	48 31 c0             	xor    rax,rax
 110:	40                   	rex
 111:	40                   	rex
 112:	40                   	rex
 113:	40                   	rex
 114:	40                   	rex
 115:	40                   	rex
 116:	40                   	rex
 117:	40                   	rex
 118:	40                   	rex
 119:	40                   	rex
 11a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 34.0
- Core cycles: 16.03
- Reference cycles: 12.05
- UOPS_EXECUTED.THREAD: 65.01
- RETIRE_SLOTS: 81.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.01
- UOPS_PORT_0: 9.27
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 10.23
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 13.45
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   7:	48 31 c0             	xor    rax,rax
   a:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
   f:	48 31 c0             	xor    rax,rax
  12:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  17:	48 31 c0             	xor    rax,rax
  1a:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  1f:	48 31 c0             	xor    rax,rax
  22:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  27:	48 31 c0             	xor    rax,rax
  2a:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  2f:	48 31 c0             	xor    rax,rax
  32:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  37:	48 31 c0             	xor    rax,rax
  3a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  3f:	48 31 c0             	xor    rax,rax
  42:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  47:	48 31 c0             	xor    rax,rax
  4a:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  4f:	48 31 c0             	xor    rax,rax
  52:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  57:	48 31 c0             	xor    rax,rax
  5a:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  5f:	48 31 c0             	xor    rax,rax
  62:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  67:	48 31 c0             	xor    rax,rax
  6a:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  6f:	48 31 c0             	xor    rax,rax
  72:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
  77:	48 31 c0             	xor    rax,rax
  7a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 32.2
- Core cycles: 16.02
- Reference cycles: 12.05
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 80.1
- UOPS_MITE: 1.28
- UOPS_MS: 0.03
- UOPS_PORT_0: 9.12
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 9.51
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 13.46
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	48 31 c0             	xor    rax,rax
   3:	40                   	rex
   4:	40                   	rex
   5:	40                   	rex
   6:	40                   	rex
   7:	40                   	rex
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	40                   	rex
   d:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
  11:	48 31 c0             	xor    rax,rax
  14:	40                   	rex
  15:	40                   	rex
  16:	40                   	rex
  17:	40                   	rex
  18:	40                   	rex
  19:	40                   	rex
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	43 f7 6c 2e 04       	imul   DWORD PTR [r14+r13*1+0x4]
  23:	48 31 c0             	xor    rax,rax
  26:	40                   	rex
  27:	40                   	rex
  28:	40                   	rex
  29:	40                   	rex
  2a:	40                   	rex
  2b:	40                   	rex
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	43 f7 6c 2e 08       	imul   DWORD PTR [r14+r13*1+0x8]
  35:	48 31 c0             	xor    rax,rax
  38:	40                   	rex
  39:	40                   	rex
  3a:	40                   	rex
  3b:	40                   	rex
  3c:	40                   	rex
  3d:	40                   	rex
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	43 f7 6c 2e 0c       	imul   DWORD PTR [r14+r13*1+0xc]
  47:	48 31 c0             	xor    rax,rax
  4a:	40                   	rex
  4b:	40                   	rex
  4c:	40                   	rex
  4d:	40                   	rex
  4e:	40                   	rex
  4f:	40                   	rex
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	43 f7 6c 2e 10       	imul   DWORD PTR [r14+r13*1+0x10]
  59:	48 31 c0             	xor    rax,rax
  5c:	40                   	rex
  5d:	40                   	rex
  5e:	40                   	rex
  5f:	40                   	rex
  60:	40                   	rex
  61:	40                   	rex
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	43 f7 6c 2e 14       	imul   DWORD PTR [r14+r13*1+0x14]
  6b:	48 31 c0             	xor    rax,rax
  6e:	40                   	rex
  6f:	40                   	rex
  70:	40                   	rex
  71:	40                   	rex
  72:	40                   	rex
  73:	40                   	rex
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	43 f7 6c 2e 18       	imul   DWORD PTR [r14+r13*1+0x18]
  7d:	48 31 c0             	xor    rax,rax
  80:	40                   	rex
  81:	40                   	rex
  82:	40                   	rex
  83:	40                   	rex
  84:	40                   	rex
  85:	40                   	rex
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	43 f7 6c 2e 1c       	imul   DWORD PTR [r14+r13*1+0x1c]
  8f:	48 31 c0             	xor    rax,rax
  92:	40                   	rex
  93:	40                   	rex
  94:	40                   	rex
  95:	40                   	rex
  96:	40                   	rex
  97:	40                   	rex
  98:	40                   	rex
  99:	40                   	rex
  9a:	40                   	rex
  9b:	40                   	rex
  9c:	43 f7 6c 2e 20       	imul   DWORD PTR [r14+r13*1+0x20]
  a1:	48 31 c0             	xor    rax,rax
  a4:	40                   	rex
  a5:	40                   	rex
  a6:	40                   	rex
  a7:	40                   	rex
  a8:	40                   	rex
  a9:	40                   	rex
  aa:	40                   	rex
  ab:	40                   	rex
  ac:	40                   	rex
  ad:	40                   	rex
  ae:	43 f7 6c 2e 24       	imul   DWORD PTR [r14+r13*1+0x24]
  b3:	48 31 c0             	xor    rax,rax
  b6:	40                   	rex
  b7:	40                   	rex
  b8:	40                   	rex
  b9:	40                   	rex
  ba:	40                   	rex
  bb:	40                   	rex
  bc:	40                   	rex
  bd:	40                   	rex
  be:	40                   	rex
  bf:	40                   	rex
  c0:	43 f7 6c 2e 28       	imul   DWORD PTR [r14+r13*1+0x28]
  c5:	48 31 c0             	xor    rax,rax
  c8:	40                   	rex
  c9:	40                   	rex
  ca:	40                   	rex
  cb:	40                   	rex
  cc:	40                   	rex
  cd:	40                   	rex
  ce:	40                   	rex
  cf:	40                   	rex
  d0:	40                   	rex
  d1:	40                   	rex
  d2:	43 f7 6c 2e 2c       	imul   DWORD PTR [r14+r13*1+0x2c]
  d7:	48 31 c0             	xor    rax,rax
  da:	40                   	rex
  db:	40                   	rex
  dc:	40                   	rex
  dd:	40                   	rex
  de:	40                   	rex
  df:	40                   	rex
  e0:	40                   	rex
  e1:	40                   	rex
  e2:	40                   	rex
  e3:	40                   	rex
  e4:	43 f7 6c 2e 30       	imul   DWORD PTR [r14+r13*1+0x30]
  e9:	48 31 c0             	xor    rax,rax
  ec:	40                   	rex
  ed:	40                   	rex
  ee:	40                   	rex
  ef:	40                   	rex
  f0:	40                   	rex
  f1:	40                   	rex
  f2:	40                   	rex
  f3:	40                   	rex
  f4:	40                   	rex
  f5:	40                   	rex
  f6:	43 f7 6c 2e 34       	imul   DWORD PTR [r14+r13*1+0x34]
  fb:	48 31 c0             	xor    rax,rax
  fe:	40                   	rex
  ff:	40                   	rex
 100:	40                   	rex
 101:	40                   	rex
 102:	40                   	rex
 103:	40                   	rex
 104:	40                   	rex
 105:	40                   	rex
 106:	40                   	rex
 107:	40                   	rex
 108:	43 f7 6c 2e 38       	imul   DWORD PTR [r14+r13*1+0x38]
 10d:	48 31 c0             	xor    rax,rax
 110:	40                   	rex
 111:	40                   	rex
 112:	40                   	rex
 113:	40                   	rex
 114:	40                   	rex
 115:	40                   	rex
 116:	40                   	rex
 117:	40                   	rex
 118:	40                   	rex
 119:	40                   	rex
 11a:	43 f7 6c 2e 3c       	imul   DWORD PTR [r14+r13*1+0x3c]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 32.2
- Core cycles: 16.01
- Reference cycles: 12.03
- UOPS_EXECUTED.THREAD: 64.1
- RETIRE_SLOTS: 80.1
- UOPS_MITE: 1.09
- UOPS_MS: 0.03
- UOPS_PORT_0: 9.11
- UOPS_PORT_1: 16.0
- UOPS_PORT_6: 9.49
- UOPS_PORT_49: 0.0
- UOPS_PORT_78: 0.0
- UOPS_PORT_5B: 13.42
- UOPS_PORT_5B>=2: 0.0
- UOPS_PORT_23A: 16.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

IMUL (M32) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With additional dependency-breaking instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With unroll_count=500, no inner loop, and 4 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With additional dependency-breaking instructions

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With additional dependency-breaking instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2