IMUL (M32)

Experiment 1

Instruction: IMUL dword ptr [R14]
Chain instructions: MOVSX RAX, EAX;XOR R14, RAX;XOR R14, RAX;XOR R14, RAX;XOR R14, RAX;XOR R14, RAX;XOR R14, RAX;XOR R14, RAX;XOR R14, RAX;XOR R14, RAX;XOR R14, RAX
Chain latency: 11

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	48 63 c0             	movsxd rax,eax
   6:	49 31 c6             	xor    r14,rax
   9:	49 31 c6             	xor    r14,rax
   c:	49 31 c6             	xor    r14,rax
   f:	49 31 c6             	xor    r14,rax
  12:	49 31 c6             	xor    r14,rax
  15:	49 31 c6             	xor    r14,rax
  18:	49 31 c6             	xor    r14,rax
  1b:	49 31 c6             	xor    r14,rax
  1e:	49 31 c6             	xor    r14,rax
  21:	49 31 c6             	xor    r14,rax

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 21.01
- Reference cycles: 21.02
- UOPS_RETIRED.ANY: 15.0

Latency operand 1 → 2 (address, index register): 10

Experiment 1

Instruction: IMUL dword ptr [R14+R13]
Chain instructions: MOVSX RAX, EAX;XOR R13, RAX;XOR R13, RAX;XOR R13, RAX;XOR R13, RAX;XOR R13, RAX;XOR R13, RAX;XOR R13, RAX;XOR R13, RAX;XOR R13, RAX;XOR R13, RAX
Chain latency: 11

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	48 63 c0             	movsxd rax,eax
   7:	49 31 c5             	xor    r13,rax
   a:	49 31 c5             	xor    r13,rax
   d:	49 31 c5             	xor    r13,rax
  10:	49 31 c5             	xor    r13,rax
  13:	49 31 c5             	xor    r13,rax
  16:	49 31 c5             	xor    r13,rax
  19:	49 31 c5             	xor    r13,rax
  1c:	49 31 c5             	xor    r13,rax
  1f:	49 31 c5             	xor    r13,rax
  22:	49 31 c5             	xor    r13,rax

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 21.0
- Reference cycles: 21.05
- UOPS_RETIRED.ANY: 15.0

Latency operand 1 → 2 (memory): ≤7

Experiment 1

Instruction: IMUL dword ptr [R14]
Chain instructions: MOVSX R12, EAX;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥11

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	4c 63 e0             	movsxd r12,eax
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 18.0
- Reference cycles: 17.99
- UOPS_RETIRED.ANY: 15.0

Latency operand 1 → 3 (address, base register): 10

Experiment 1

Instruction: IMUL dword ptr [R14]
Chain instructions: MOVSX RDX, EDX;XOR R14, RDX;XOR R14, RDX;XOR R14, RDX;XOR R14, RDX;XOR R14, RDX;XOR R14, RDX;XOR R14, RDX;XOR R14, RDX;XOR R14, RDX;XOR R14, RDX
Chain latency: 11

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	48 63 d2             	movsxd rdx,edx
   6:	49 31 d6             	xor    r14,rdx
   9:	49 31 d6             	xor    r14,rdx
   c:	49 31 d6             	xor    r14,rdx
   f:	49 31 d6             	xor    r14,rdx
  12:	49 31 d6             	xor    r14,rdx
  15:	49 31 d6             	xor    r14,rdx
  18:	49 31 d6             	xor    r14,rdx
  1b:	49 31 d6             	xor    r14,rdx
  1e:	49 31 d6             	xor    r14,rdx
  21:	49 31 d6             	xor    r14,rdx

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 20.97
- Reference cycles: 20.97
- UOPS_RETIRED.ANY: 15.0

Latency operand 1 → 3 (address, index register): 10

Experiment 1

Instruction: IMUL dword ptr [R14+R13]
Chain instructions: MOVSX RDX, EDX;XOR R13, RDX;XOR R13, RDX;XOR R13, RDX;XOR R13, RDX;XOR R13, RDX;XOR R13, RDX;XOR R13, RDX;XOR R13, RDX;XOR R13, RDX;XOR R13, RDX
Chain latency: 11

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	48 63 d2             	movsxd rdx,edx
   7:	49 31 d5             	xor    r13,rdx
   a:	49 31 d5             	xor    r13,rdx
   d:	49 31 d5             	xor    r13,rdx
  10:	49 31 d5             	xor    r13,rdx
  13:	49 31 d5             	xor    r13,rdx
  16:	49 31 d5             	xor    r13,rdx
  19:	49 31 d5             	xor    r13,rdx
  1c:	49 31 d5             	xor    r13,rdx
  1f:	49 31 d5             	xor    r13,rdx
  22:	49 31 d5             	xor    r13,rdx

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 21.0
- Reference cycles: 20.96
- UOPS_RETIRED.ANY: 15.0

Latency operand 1 → 3 (memory): ≤7

Experiment 1

Instruction: IMUL dword ptr [R14]
Chain instructions: MOVSX R12, EDX;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥11

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	4c 63 e2             	movsxd r12,edx
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 18.0
- Reference cycles: 17.97
- UOPS_RETIRED.ANY: 15.0

Latency operand 1 → 4 (address, base register): 10

Experiment 1

Instruction: IMUL dword ptr [R14]
Chain instruction: CMOVO R14, R14
Chain latency: 2

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	4d 0f 40 f6          	cmovo  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 12.01
- Reference cycles: 12.02
- UOPS_RETIRED.ANY: 5.0

Experiment 2 (with dependency-breaking instructions)

Instruction: IMUL dword ptr [R14]
Chain instructions: CMOVO R14, R14;MOV EAX, 0
Chain latency: 2

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	4d 0f 40 f6          	cmovo  r14,r14
   7:	b8 00 00 00 00       	mov    eax,0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 12.0
- Reference cycles: 12.0
- UOPS_RETIRED.ANY: 6.0

Experiment 3

Instruction: IMUL dword ptr [R14]
Chain instruction: CMOVC R14, R14
Chain latency: 2

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	4d 0f 42 f6          	cmovb  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 12.0
- Reference cycles: 12.03
- UOPS_RETIRED.ANY: 5.0

Experiment 4 (with dependency-breaking instructions)

Instruction: IMUL dword ptr [R14]
Chain instructions: CMOVC R14, R14;MOV EAX, 0
Chain latency: 2

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	4d 0f 42 f6          	cmovb  r14,r14
   7:	b8 00 00 00 00       	mov    eax,0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 12.0
- Reference cycles: 12.02
- UOPS_RETIRED.ANY: 6.0

Latency operand 1 → 4 (address, index register): 10

Experiment 1

Instruction: IMUL dword ptr [R14+R13]
Chain instruction: CMOVO R13, R13
Chain latency: 2

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	4d 0f 40 ed          	cmovo  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 12.0
- Reference cycles: 12.03
- UOPS_RETIRED.ANY: 5.0

Experiment 2 (with dependency-breaking instructions)

Instruction: IMUL dword ptr [R14+R13]
Chain instructions: CMOVO R13, R13;MOV EAX, 0
Chain latency: 2

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	4d 0f 40 ed          	cmovo  r13,r13
   8:	b8 00 00 00 00       	mov    eax,0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 12.0
- Reference cycles: 12.06
- UOPS_RETIRED.ANY: 6.0

Experiment 3

Instruction: IMUL dword ptr [R14+R13]
Chain instruction: CMOVC R13, R13
Chain latency: 2

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	4d 0f 42 ed          	cmovb  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 12.0
- Reference cycles: 12.06
- UOPS_RETIRED.ANY: 5.0

Experiment 4 (with dependency-breaking instructions)

Instruction: IMUL dword ptr [R14+R13]
Chain instructions: CMOVC R13, R13;MOV EAX, 0
Chain latency: 2

Code:

   0:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]
   4:	4d 0f 42 ed          	cmovb  r13,r13
   8:	b8 00 00 00 00       	mov    eax,0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 12.0
- Reference cycles: 12.05
- UOPS_RETIRED.ANY: 6.0

Latency operand 1 → 4 (memory): ≤7

Experiment 1

Instruction: IMUL dword ptr [R14]
Chain instructions: CMOVO R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥13

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	4d 0f 40 e4          	cmovo  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 20.01
- Reference cycles: 20.03
- UOPS_RETIRED.ANY: 16.0

Experiment 2

Instruction: IMUL dword ptr [R14]
Chain instructions: CMOVC R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥13

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	4d 0f 42 e4          	cmovb  r12,r12
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 20.0
- Reference cycles: 20.04
- UOPS_RETIRED.ANY: 16.0

Latency operand 2 → 2: 7

Experiment 1

Instruction: IMUL dword ptr [R14]

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.99
- Reference cycles: 7.01
- UOPS_RETIRED.ANY: 4.0

Experiment 2

Instruction: IMUL dword ptr [R14]
Chain instructions: MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX
Chain latency: 11

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	48 63 c0             	movsxd rax,eax
   6:	48 63 c0             	movsxd rax,eax
   9:	48 63 c0             	movsxd rax,eax
   c:	48 63 c0             	movsxd rax,eax
   f:	48 63 c0             	movsxd rax,eax
  12:	48 63 c0             	movsxd rax,eax
  15:	48 63 c0             	movsxd rax,eax
  18:	48 63 c0             	movsxd rax,eax
  1b:	48 63 c0             	movsxd rax,eax
  1e:	48 63 c0             	movsxd rax,eax
  21:	48 63 c0             	movsxd rax,eax

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 18.0
- Reference cycles: 17.97
- UOPS_RETIRED.ANY: 15.0

Latency operand 2 → 3: 7

Experiment 1

Instruction: IMUL dword ptr [R14]
Chain instructions: MOVSX RAX, EDX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX
Chain latency: 11

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	48 63 c2             	movsxd rax,edx
   6:	48 63 c0             	movsxd rax,eax
   9:	48 63 c0             	movsxd rax,eax
   c:	48 63 c0             	movsxd rax,eax
   f:	48 63 c0             	movsxd rax,eax
  12:	48 63 c0             	movsxd rax,eax
  15:	48 63 c0             	movsxd rax,eax
  18:	48 63 c0             	movsxd rax,eax
  1b:	48 63 c0             	movsxd rax,eax
  1e:	48 63 c0             	movsxd rax,eax
  21:	48 63 c0             	movsxd rax,eax

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 18.0
- Reference cycles: 17.97
- UOPS_RETIRED.ANY: 15.0

Latency operand 2 → 4: 7

Experiment 1

Instruction: IMUL dword ptr [R14]
Chain instructions: CMOVO R15D, R15D;MOVSX RAX, R15D;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX
Chain latency: 13

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	45 0f 40 ff          	cmovo  r15d,r15d
   7:	49 63 c7             	movsxd rax,r15d
   a:	48 63 c0             	movsxd rax,eax
   d:	48 63 c0             	movsxd rax,eax
  10:	48 63 c0             	movsxd rax,eax
  13:	48 63 c0             	movsxd rax,eax
  16:	48 63 c0             	movsxd rax,eax
  19:	48 63 c0             	movsxd rax,eax
  1c:	48 63 c0             	movsxd rax,eax
  1f:	48 63 c0             	movsxd rax,eax
  22:	48 63 c0             	movsxd rax,eax
  25:	48 63 c0             	movsxd rax,eax

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 20.0
- Reference cycles: 20.01
- UOPS_RETIRED.ANY: 16.0

Experiment 2

Instruction: IMUL dword ptr [R14]
Chain instructions: CMOVC R15D, R15D;MOVSX RAX, R15D;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX;MOVSX RAX, EAX
Chain latency: 13

Code:

   0:	41 f7 2e             	imul   DWORD PTR [r14]
   3:	45 0f 42 ff          	cmovb  r15d,r15d
   7:	49 63 c7             	movsxd rax,r15d
   a:	48 63 c0             	movsxd rax,eax
   d:	48 63 c0             	movsxd rax,eax
  10:	48 63 c0             	movsxd rax,eax
  13:	48 63 c0             	movsxd rax,eax
  16:	48 63 c0             	movsxd rax,eax
  19:	48 63 c0             	movsxd rax,eax
  1c:	48 63 c0             	movsxd rax,eax
  1f:	48 63 c0             	movsxd rax,eax
  22:	48 63 c0             	movsxd rax,eax
  25:	48 63 c0             	movsxd rax,eax

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 20.0
- Reference cycles: 20.01
- UOPS_RETIRED.ANY: 16.0

IMUL (M32) - Latency

Operands

Latency operand 1 → 2 (address, base register): 10

Latency operand 1 → 2 (address, index register): 10

Latency operand 1 → 2 (memory): ≤7

Latency operand 1 → 3 (address, base register): 10

Latency operand 1 → 3 (address, index register): 10

Latency operand 1 → 3 (memory): ≤7

Latency operand 1 → 4 (address, base register): 10

Latency operand 1 → 4 (address, index register): 10

Latency operand 1 → 4 (memory): ≤7

Latency operand 2 → 2: 7

Latency operand 2 → 3: 7

Latency operand 2 → 4: 7

Latency operand 1 → 2 (address, base register): 10

Experiment 1

Latency operand 1 → 2 (address, index register): 10

Experiment 1

Latency operand 1 → 2 (memory): ≤7

Experiment 1

Latency operand 1 → 3 (address, base register): 10

Experiment 1

Latency operand 1 → 3 (address, index register): 10

Experiment 1

Latency operand 1 → 3 (memory): ≤7

Experiment 1

Latency operand 1 → 4 (address, base register): 10

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Latency operand 1 → 4 (address, index register): 10

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Latency operand 1 → 4 (memory): ≤7

Experiment 1

Experiment 2

Latency operand 2 → 2: 7

Experiment 1

Experiment 2

Latency operand 2 → 3: 7

Experiment 1

Latency operand 2 → 4: 7

Experiment 1

Experiment 2