IMUL (M32) - Port Usage

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	41 f7 2e             	imul   DWORD PTR [r14]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.08
- Reference cycles: 11.63
- UOPS_PORT_1: 11.0

⇨ One μop that can only use port '1'

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 41 c1 c0 00       	rol    r8w,0x0
  26:	66 41 c1 c1 00       	rol    r9w,0x0
  2b:	66 41 c1 c2 00       	rol    r10w,0x0
  30:	66 41 c1 c3 00       	rol    r11w,0x0
  35:	66 41 c1 c4 00       	rol    r12w,0x0
  3a:	66 c1 c3 00          	rol    bx,0x0
  3e:	66 c1 c1 00          	rol    cx,0x0
  42:	66 41 c1 c0 00       	rol    r8w,0x0
  47:	66 41 c1 c1 00       	rol    r9w,0x0
  4c:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.56
- Reference cycles: 9.03
- UOPS_PORT_6: 8.48
- UOPS_PORT_0: 8.5

⇨ One μop that can only use ports {'0', '6'}

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	41 f7 2e             	imul   DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.73
- Reference cycles: 9.03
- UOPS_PORT_2: 8.5
- UOPS_PORT_3: 8.5

⇨ One μop that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	f3 0f d6 c0          	movq2dq xmm0,mm0
   4:	f3 0f d6 c8          	movq2dq xmm1,mm0
   8:	f3 0f d6 d0          	movq2dq xmm2,mm0
   c:	f3 0f d6 d8          	movq2dq xmm3,mm0
  10:	f3 0f d6 e0          	movq2dq xmm4,mm0
  14:	f3 0f d6 e8          	movq2dq xmm5,mm0
  18:	f3 0f d6 f0          	movq2dq xmm6,mm0
  1c:	f3 0f d6 f8          	movq2dq xmm7,mm0
  20:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  25:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  2a:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  2f:	f3 44 0f d6 d8       	movq2dq xmm11,mm0
  34:	f3 44 0f d6 e0       	movq2dq xmm12,mm0
  39:	f3 0f d6 c0          	movq2dq xmm0,mm0
  3d:	f3 0f d6 c8          	movq2dq xmm1,mm0
  41:	f3 0f d6 d0          	movq2dq xmm2,mm0
  45:	f3 0f d6 d8          	movq2dq xmm3,mm0
  49:	f3 0f d6 e0          	movq2dq xmm4,mm0
  4d:	f3 0f d6 e8          	movq2dq xmm5,mm0
  51:	f3 0f d6 f0          	movq2dq xmm6,mm0
  55:	f3 0f d6 f8          	movq2dq xmm7,mm0
  59:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  5e:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  63:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  68:	41 f7 2e             	imul   DWORD PTR [r14]

Init:
```
VZEROALL;
PXOR MM0, MM0
```
Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 8.59
- Reference cycles: 9.11
- UOPS_PORT_1: 8.34
- UOPS_PORT_0: 8.34
- UOPS_PORT_5: 8.34

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 0f bf c1          	movsx  r8d,r9w
   4:	45 0f bf d1          	movsx  r10d,r9w
   8:	45 0f bf d9          	movsx  r11d,r9w
   c:	45 0f bf e1          	movsx  r12d,r9w
  10:	41 0f bf d9          	movsx  ebx,r9w
  14:	41 0f bf c9          	movsx  ecx,r9w
  18:	45 0f bf c1          	movsx  r8d,r9w
  1c:	45 0f bf d1          	movsx  r10d,r9w
  20:	45 0f bf d9          	movsx  r11d,r9w
  24:	45 0f bf e1          	movsx  r12d,r9w
  28:	41 0f bf d9          	movsx  ebx,r9w
  2c:	41 0f bf c9          	movsx  ecx,r9w
  30:	45 0f bf c1          	movsx  r8d,r9w
  34:	45 0f bf d1          	movsx  r10d,r9w
  38:	45 0f bf d9          	movsx  r11d,r9w
  3c:	45 0f bf e1          	movsx  r12d,r9w
  40:	41 0f bf d9          	movsx  ebx,r9w
  44:	41 0f bf c9          	movsx  ecx,r9w
  48:	45 0f bf c1          	movsx  r8d,r9w
  4c:	45 0f bf d1          	movsx  r10d,r9w
  50:	45 0f bf d9          	movsx  r11d,r9w
  54:	45 0f bf e1          	movsx  r12d,r9w
  58:	41 0f bf d9          	movsx  ebx,r9w
  5c:	41 0f bf c9          	movsx  ecx,r9w
  60:	45 0f bf c1          	movsx  r8d,r9w
  64:	45 0f bf d1          	movsx  r10d,r9w
  68:	45 0f bf d9          	movsx  r11d,r9w
  6c:	45 0f bf e1          	movsx  r12d,r9w
  70:	41 0f bf d9          	movsx  ebx,r9w
  74:	41 0f bf c9          	movsx  ecx,r9w
  78:	45 0f bf c1          	movsx  r8d,r9w
  7c:	45 0f bf d1          	movsx  r10d,r9w
  80:	41 f7 2e             	imul   DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 33.0
- Core cycles: 9.35
- Reference cycles: 9.68
- UOPS_PORT_1: 8.06
- UOPS_PORT_0: 8.87
- UOPS_PORT_5: 9.0
- UOPS_PORT_6: 9.06

⇨ One μop that can only use ports {'0', '1', '5', '6'}

With an indexed addressing mode

With blocking instructions for port '1':

Code:

   0:	66 0f 58 c1          	addpd  xmm0,xmm1
   4:	66 0f 58 d1          	addpd  xmm2,xmm1
   8:	66 0f 58 d9          	addpd  xmm3,xmm1
   c:	66 0f 58 e1          	addpd  xmm4,xmm1
  10:	66 0f 58 e9          	addpd  xmm5,xmm1
  14:	66 0f 58 f1          	addpd  xmm6,xmm1
  18:	66 0f 58 f9          	addpd  xmm7,xmm1
  1c:	66 44 0f 58 c1       	addpd  xmm8,xmm1
  21:	66 44 0f 58 c9       	addpd  xmm9,xmm1
  26:	66 44 0f 58 d1       	addpd  xmm10,xmm1
  2b:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:

VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
MOVUPD XMM2, [R14];
MOVUPD XMM3, [R14];
MOVUPD XMM4, [R14];
MOVUPD XMM5, [R14];
MOVUPD XMM6, [R14];
MOVUPD XMM7, [R14];
MOVUPD XMM8, [R14];
MOVUPD XMM9, [R14];
MOVUPD XMM10, [R14];
MOVUPD XMM11, [R14];
MOVUPD XMM12, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.08
- Reference cycles: 11.67
- UOPS_PORT_1: 11.0

⇨ One μop that can only use port '1'

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 41 c1 c0 00       	rol    r8w,0x0
  26:	66 41 c1 c1 00       	rol    r9w,0x0
  2b:	66 41 c1 c2 00       	rol    r10w,0x0
  30:	66 41 c1 c3 00       	rol    r11w,0x0
  35:	66 41 c1 c4 00       	rol    r12w,0x0
  3a:	66 c1 c3 00          	rol    bx,0x0
  3e:	66 c1 c1 00          	rol    cx,0x0
  42:	66 41 c1 c0 00       	rol    r8w,0x0
  47:	66 41 c1 c1 00       	rol    r9w,0x0
  4c:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.56
- Reference cycles: 9.03
- UOPS_PORT_6: 8.47
- UOPS_PORT_0: 8.52

⇨ One μop that can only use ports {'0', '6'}

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	f2 45 0f f0 96 e0 00 	lddqu  xmm10,[r14+0xe0]
  55:	00 00 
  57:	f2 45 0f f0 9e f0 00 	lddqu  xmm11,[r14+0xf0]
  5e:	00 00 
  60:	f2 45 0f f0 a6 00 01 	lddqu  xmm12,[r14+0x100]
  67:	00 00 
  69:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
  6f:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
  75:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  7b:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 17.0
- Core cycles: 8.76
- Reference cycles: 9.19
- UOPS_PORT_2: 8.5
- UOPS_PORT_3: 8.5

⇨ One μop that can only use ports {'2', '3'}

With blocking instructions for ports {'0', '1', '5'}:

Code:

   0:	f3 0f d6 c0          	movq2dq xmm0,mm0
   4:	f3 0f d6 c8          	movq2dq xmm1,mm0
   8:	f3 0f d6 d0          	movq2dq xmm2,mm0
   c:	f3 0f d6 d8          	movq2dq xmm3,mm0
  10:	f3 0f d6 e0          	movq2dq xmm4,mm0
  14:	f3 0f d6 e8          	movq2dq xmm5,mm0
  18:	f3 0f d6 f0          	movq2dq xmm6,mm0
  1c:	f3 0f d6 f8          	movq2dq xmm7,mm0
  20:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  25:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  2a:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  2f:	f3 44 0f d6 d8       	movq2dq xmm11,mm0
  34:	f3 44 0f d6 e0       	movq2dq xmm12,mm0
  39:	f3 0f d6 c0          	movq2dq xmm0,mm0
  3d:	f3 0f d6 c8          	movq2dq xmm1,mm0
  41:	f3 0f d6 d0          	movq2dq xmm2,mm0
  45:	f3 0f d6 d8          	movq2dq xmm3,mm0
  49:	f3 0f d6 e0          	movq2dq xmm4,mm0
  4d:	f3 0f d6 e8          	movq2dq xmm5,mm0
  51:	f3 0f d6 f0          	movq2dq xmm6,mm0
  55:	f3 0f d6 f8          	movq2dq xmm7,mm0
  59:	f3 44 0f d6 c0       	movq2dq xmm8,mm0
  5e:	f3 44 0f d6 c8       	movq2dq xmm9,mm0
  63:	f3 44 0f d6 d0       	movq2dq xmm10,mm0
  68:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
PXOR MM0, MM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 8.59
- Reference cycles: 9.11
- UOPS_PORT_1: 8.37
- UOPS_PORT_0: 8.32
- UOPS_PORT_5: 8.32

With blocking instructions for ports {'0', '1', '5', '6'}:

Code:

   0:	45 0f bf c1          	movsx  r8d,r9w
   4:	45 0f bf d1          	movsx  r10d,r9w
   8:	45 0f bf d9          	movsx  r11d,r9w
   c:	45 0f bf e1          	movsx  r12d,r9w
  10:	41 0f bf d9          	movsx  ebx,r9w
  14:	41 0f bf c9          	movsx  ecx,r9w
  18:	45 0f bf c1          	movsx  r8d,r9w
  1c:	45 0f bf d1          	movsx  r10d,r9w
  20:	45 0f bf d9          	movsx  r11d,r9w
  24:	45 0f bf e1          	movsx  r12d,r9w
  28:	41 0f bf d9          	movsx  ebx,r9w
  2c:	41 0f bf c9          	movsx  ecx,r9w
  30:	45 0f bf c1          	movsx  r8d,r9w
  34:	45 0f bf d1          	movsx  r10d,r9w
  38:	45 0f bf d9          	movsx  r11d,r9w
  3c:	45 0f bf e1          	movsx  r12d,r9w
  40:	41 0f bf d9          	movsx  ebx,r9w
  44:	41 0f bf c9          	movsx  ecx,r9w
  48:	45 0f bf c1          	movsx  r8d,r9w
  4c:	45 0f bf d1          	movsx  r10d,r9w
  50:	45 0f bf d9          	movsx  r11d,r9w
  54:	45 0f bf e1          	movsx  r12d,r9w
  58:	41 0f bf d9          	movsx  ebx,r9w
  5c:	41 0f bf c9          	movsx  ecx,r9w
  60:	45 0f bf c1          	movsx  r8d,r9w
  64:	45 0f bf d1          	movsx  r10d,r9w
  68:	45 0f bf d9          	movsx  r11d,r9w
  6c:	45 0f bf e1          	movsx  r12d,r9w
  70:	41 0f bf d9          	movsx  ebx,r9w
  74:	41 0f bf c9          	movsx  ecx,r9w
  78:	45 0f bf c1          	movsx  r8d,r9w
  7c:	45 0f bf d1          	movsx  r10d,r9w
  80:	43 f7 2c 2e          	imul   DWORD PTR [r14+r13*1]

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 33.0
- Core cycles: 9.42
- Reference cycles: 9.89
- UOPS_PORT_1: 8.03
- UOPS_PORT_0: 8.97
- UOPS_PORT_5: 9.0
- UOPS_PORT_6: 9.0

⇨ One μop that can only use ports {'0', '1', '5', '6'}