VPINSRQ (XMM, XMM, R64, I8)
Summary:
"Insert Byte/Dword/Qword"
Reference:
https://www.felixcloutier.com/x86/PINSRB:PINSRD:PINSRQ.html
Extension:
AVX
Category:
AVX
ISA-Set:
AVX
CPL:
3
iform:
VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb
iclass:
VPINSRQ
ASM:
VPINSRQ
Operands
Operand 1 (w): Register (XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15)
Operand 2 (r): Register (XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15)
Operand 3 (r): Register (RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, R8, R9, R10, R11, R12, R13, R14, R15)
Operand 4 (r): 8-bit immediate
Available performance data
Alder Lake-P
Alder Lake-E
Rocket Lake
Tiger Lake
Ice Lake
Cascade Lake
Cannon Lake
Skylake-X
Coffee Lake
Kaby Lake
Skylake
Broadwell
Haswell
Ivy Bridge
Sandy Bridge
AMD Zen 4
AMD Zen 3
AMD Zen 2
AMD Zen+
Alder Lake-P
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.06
Measured (unrolled):
1.06
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p15+1*p5
Alder Lake-E
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤9
Throughput
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 1
Microcode Sequencer (MS): 0
Rocket Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.07
Measured (unrolled):
1.08
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p15+1*p5
Tiger Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.07
Measured (unrolled):
1.08
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p15+1*p5
Ice Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.07
Measured (unrolled):
1.08
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p15+1*p5
Cascade Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤4
Throughput
Computed from the port usage: 2.00
Measured (loop):
2.00
Measured (unrolled):
2.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
2*p5
Cannon Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤4
Throughput
Computed from the port usage: 2.00
Measured (loop):
2.00
Measured (unrolled):
2.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
2*p5
Skylake-X
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤4
Throughput
Computed from the port usage: 2.00
Measured (loop):
2.00
Measured (unrolled):
2.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
2*p5
IACA 2.3
Throughput
Computed from the port usage: 2.00
IACA:
2.00
Number of μops:
2
Port usage:
2*p5
IACA 3.0
Throughput
Computed from the port usage: 2.00
IACA:
1.94
Number of μops:
2
Port usage:
2*p5
Coffee Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤4
Throughput
Computed from the port usage: 2.00
Measured (loop):
2.00
Measured (unrolled):
2.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
2*p5
Kaby Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤4
Throughput
Computed from the port usage: 2.00
Measured (loop):
2.00
Measured (unrolled):
2.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
2*p5
Skylake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤4
Throughput
Computed from the port usage: 2.00
Measured (loop):
2.00
Measured (unrolled):
2.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
2*p5
IACA 2.3
Throughput
Computed from the port usage: 2.00
IACA:
2.00
Number of μops:
2
Port usage:
2*p5
IACA 3.0
Throughput
Computed from the port usage: 2.00
IACA:
1.94
Number of μops:
2
Port usage:
2*p5
Broadwell
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤2
Throughput
Computed from the port usage: 2.00
Measured (loop):
2.00
Measured (unrolled):
2.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
2*p5
IACA 2.2
Throughput
Computed from the port usage: 2.00
IACA:
2.00 (with the -no_interiteration flag: 2.00)
Number of μops:
2
Port usage:
2*p5
IACA 2.3
Throughput
Computed from the port usage: 2.00
IACA:
2.00
Number of μops:
2
Port usage:
2*p5
IACA 3.0
Throughput
Computed from the port usage: 2.00
IACA:
1.95
Number of μops:
2
Port usage:
2*p5
Haswell
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤2
Throughput
Computed from the port usage: 2.00
Measured (loop):
2.00
Measured (unrolled):
2.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
2*p5
IACA 2.1
Latency:
2
Throughput
Computed from the port usage: 2.00
IACA:
2.00 (with the -no_interiteration flag: 2.00)
Number of μops:
2
Port usage:
2*p5
IACA 2.2
Throughput
Computed from the port usage: 2.00
IACA:
2.00 (with the -no_interiteration flag: 2.00)
Number of μops:
2
Port usage:
2*p5
IACA 2.3
Throughput
Computed from the port usage: 2.00
IACA:
2.00
Number of μops:
2
Port usage:
2*p5
IACA 3.0
Throughput
Computed from the port usage: 2.00
IACA:
1.94
Number of μops:
2
Port usage:
2*p5
Ivy Bridge
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤2
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.07
Measured (unrolled):
1.06
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p15+1*p5
IACA 2.1
Latency:
2
Throughput
Computed from the port usage: 1.00
IACA:
1.00 (with the -no_interiteration flag: 1.00)
Number of μops:
2
Port usage:
1*p15+1*p5
IACA 2.2
Throughput
Computed from the port usage: 1.00
IACA:
1.00 (with the -no_interiteration flag: 1.00)
Number of μops:
2
Port usage:
1*p15+1*p5
IACA 2.3
Throughput
Computed from the port usage: 1.00
IACA:
1.00
Number of μops:
2
Port usage:
1*p15+1*p5
Sandy Bridge
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤2
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.07
Measured (unrolled):
1.06
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p15+1*p5
IACA 2.1
Latency:
2
Throughput
Computed from the port usage: 1.00
IACA:
1.00 (with the -no_interiteration flag: 1.00)
Number of μops:
2
Port usage:
1*p15+1*p5
IACA 2.2
Throughput
Computed from the port usage: 1.00
IACA:
1.00 (with the -no_interiteration flag: 1.00)
Number of μops:
2
Port usage:
1*p15+1*p5
IACA 2.3
Throughput
Computed from the port usage: 1.00
IACA:
1.00
Number of μops:
2
Port usage:
1*p15+1*p5
AMD Zen 4
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤6
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Port usage:
1*FP1
AMD Zen 3
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤6
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Port usage:
1*FP1
AMD Zen 2
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤6
Throughput
Measured (loop):
1.23
Measured (unrolled):
1.23
Number of μops
Executed: 2
AMD Zen+
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
≤6
Throughput
Measured (loop):
1.23
Measured (unrolled):
1.23
Number of μops
Executed: 2