VPINSRQ (XMM, XMM, R64, I8) - Latency

Operands

Latency operand 2 → 1: 1

Latency operand 3 → 1: ≤6

Latency operand 2 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (with the same register for different operands)

Experiment 6 (with the same register for different operands)

Experiment 7 (with the same register for different operands)

Experiment 8 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 9 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 10 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Latency operand 3 → 1: ≤6

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6

Experiment 7

Experiment 8

Experiment 9

Experiment 10

Experiment 11

Experiment 12

Experiment 13

Experiment 14

Experiment 15

Experiment 16

Experiment 17

Experiment 18

Experiment 19 (source registers initialized by an instruction of the same kind)

Experiment 20 (source registers initialized by an instruction of the same kind)

Experiment 21 (source registers initialized by an instruction of the same kind)

Experiment 22 (source registers initialized by an instruction of the same kind)

Experiment 23 (source registers initialized by an instruction of the same kind)

Experiment 24 (source registers initialized by an instruction of the same kind)

Experiment 25 (source registers initialized by an instruction of the same kind)

Experiment 26 (source registers initialized by an instruction of the same kind)

Experiment 27 (source registers initialized by an instruction of the same kind)

Experiment 28 (source registers initialized by an instruction of the same kind)

Experiment 29 (source registers initialized by an instruction of the same kind)

Experiment 30 (source registers initialized by an instruction of the same kind)

Experiment 31 (source registers initialized by an instruction of the same kind)

Experiment 32 (source registers initialized by an instruction of the same kind)

Experiment 33 (source registers initialized by an instruction of the same kind)

Experiment 34 (source registers initialized by an instruction of the same kind)

Experiment 35 (source registers initialized by an instruction of the same kind)

Experiment 36 (source registers initialized by an instruction of the same kind)

Experiment 37 (with the same register for different operands)

Experiment 38 (with the same register for different operands)

Experiment 39 (with the same register for different operands)

Experiment 40 (with the same register for different operands)

Experiment 41 (with the same register for different operands)

Experiment 42 (with the same register for different operands)

Experiment 43 (with the same register for different operands)

Experiment 44 (with the same register for different operands)

Experiment 45 (with the same register for different operands)

Experiment 46 (with the same register for different operands)

Experiment 47 (with the same register for different operands)

Experiment 48 (with the same register for different operands)

Experiment 49 (with the same register for different operands)

Experiment 50 (with the same register for different operands)

Experiment 51 (with the same register for different operands)

Experiment 52 (with the same register for different operands)

Experiment 53 (with the same register for different operands)

Experiment 54 (with the same register for different operands)

Experiment 55 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 56 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 57 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 58 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 59 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 60 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 61 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 62 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 63 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 64 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 65 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 66 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 67 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 68 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 69 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 70 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 71 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 72 (source registers initialized by an instruction of the same kind, with the same register for different operands)