VPINSRQ (XMM, XMM, R64, I8)

Experiment 1

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTSD2SI R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 7b 2d c0          	vcvtsd2si r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.0
- UOPS_EXECUTED.THREAD: 4.0

Experiment 2

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTSD2SI R8, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 61 fb 2d c0       	vcvtsd2si r8,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.1
- UOPS_EXECUTED.THREAD: 4.0

Experiment 3

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTSS2SI R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 7a 2d c0          	vcvtss2si r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 2.95
- UOPS_EXECUTED.THREAD: 4.0

Experiment 4

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTSS2SI R8, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 61 fa 2d c0       	vcvtss2si r8,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 10.0
- Reference cycles: 3.31
- UOPS_EXECUTED.THREAD: 5.0

Experiment 5

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTTSD2SI R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 7b 2c c0          	vcvttsd2si r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.05
- UOPS_EXECUTED.THREAD: 4.0

Experiment 6

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTTSD2SI R8, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 61 fb 2c c0       	vcvttsd2si r8,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.05
- UOPS_EXECUTED.THREAD: 4.0

Experiment 7

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTTSS2SI R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 7a 2c c0          	vcvttss2si r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.05
- UOPS_EXECUTED.THREAD: 4.0

Experiment 8

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTTSS2SI R8, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 61 fa 2c c0       	vcvttss2si r8,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 10.0
- Reference cycles: 3.26
- UOPS_EXECUTED.THREAD: 5.0

Experiment 9

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VEXTRACTPS R8D, XMM0, 2
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 c3 79 17 c0 02    	vextractps r8d,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 2.12
- UOPS_EXECUTED.THREAD: 4.0

Experiment 10

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VMOVD R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 c1 79 7e c0       	vmovd  r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.0
- Reference cycles: 1.76
- UOPS_EXECUTED.THREAD: 2.99

Experiment 11

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VMOVMSKPD R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 79 50 c0          	vmovmskpd r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.0
- Reference cycles: 1.6
- UOPS_EXECUTED.THREAD: 3.0

Experiment 12

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VMOVMSKPS R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 78 50 c0          	vmovmskps r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.0
- Reference cycles: 1.81
- UOPS_EXECUTED.THREAD: 3.0

Experiment 13

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VMOVQ R8, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 c1 f9 7e c0       	vmovq  r8,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.0
- Reference cycles: 1.71
- UOPS_EXECUTED.THREAD: 3.0

Experiment 14

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VPEXTRB R8D, XMM0, 2
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 c3 79 14 c0 02    	vpextrb r8d,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.99
- Reference cycles: 2.12
- UOPS_EXECUTED.THREAD: 4.0

Experiment 15

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VPEXTRD R8D, XMM0, 2
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 c3 79 16 c0 02    	vpextrd r8d,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 2.17
- UOPS_EXECUTED.THREAD: 4.0

Experiment 16

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VPEXTRQ R8, XMM0, 2
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 c3 f9 16 c0 02    	vpextrq r8,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 1.86
- UOPS_EXECUTED.THREAD: 4.0

Experiment 17

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VPEXTRW R8D, XMM0, 2
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 79 c5 c0 02       	vpextrw r8d,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.99
- Reference cycles: 2.07
- UOPS_EXECUTED.THREAD: 4.0

Experiment 18

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VPMOVMSKB R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 79 d7 c0          	vpmovmskb r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.0
- Reference cycles: 1.71
- UOPS_EXECUTED.THREAD: 3.0

Experiment 19 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTSD2SI R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 7b 2d c0          	vcvtsd2si r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.0
- UOPS_EXECUTED.THREAD: 4.0

Experiment 20 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTSD2SI R8, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 61 fb 2d c0       	vcvtsd2si r8,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.05
- UOPS_EXECUTED.THREAD: 4.0

Experiment 21 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTSS2SI R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 7a 2d c0          	vcvtss2si r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.0
- UOPS_EXECUTED.THREAD: 4.0

Experiment 22 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTSS2SI R8, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 61 fa 2d c0       	vcvtss2si r8,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 10.0
- Reference cycles: 3.26
- UOPS_EXECUTED.THREAD: 5.0

Experiment 23 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTTSD2SI R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 7b 2c c0          	vcvttsd2si r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.05
- UOPS_EXECUTED.THREAD: 4.0

Experiment 24 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTTSD2SI R8, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 61 fb 2c c0       	vcvttsd2si r8,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.0
- UOPS_EXECUTED.THREAD: 4.0

Experiment 25 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTTSS2SI R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 7a 2c c0          	vcvttss2si r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 9.0
- Reference cycles: 3.05
- UOPS_EXECUTED.THREAD: 4.0

Experiment 26 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VCVTTSS2SI R8, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 61 fa 2c c0       	vcvttss2si r8,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 10.0
- Reference cycles: 3.2
- UOPS_EXECUTED.THREAD: 5.0

Experiment 27 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VEXTRACTPS R8D, XMM0, 2
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 c3 79 17 c0 02    	vextractps r8d,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 2.12
- UOPS_EXECUTED.THREAD: 4.0

Experiment 28 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VMOVD R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 c1 79 7e c0       	vmovd  r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.0
- Reference cycles: 1.55
- UOPS_EXECUTED.THREAD: 3.0

Experiment 29 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VMOVMSKPD R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 79 50 c0          	vmovmskpd r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.05
- Reference cycles: 1.71
- UOPS_EXECUTED.THREAD: 3.05

Experiment 30 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VMOVMSKPS R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 78 50 c0          	vmovmskps r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.0
- Reference cycles: 1.71
- UOPS_EXECUTED.THREAD: 3.0

Experiment 31 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VMOVQ R8, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 c1 f9 7e c0       	vmovq  r8,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.99
- Reference cycles: 1.71
- UOPS_EXECUTED.THREAD: 3.0

Experiment 32 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VPEXTRB R8D, XMM0, 2
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 c3 79 14 c0 02    	vpextrb r8d,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 2.02
- UOPS_EXECUTED.THREAD: 4.0

Experiment 33 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VPEXTRD R8D, XMM0, 2
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 c3 79 16 c0 02    	vpextrd r8d,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 1.96
- UOPS_EXECUTED.THREAD: 4.0

Experiment 34 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VPEXTRQ R8, XMM0, 2
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c4 c3 f9 16 c0 02    	vpextrq r8,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 1.96
- UOPS_EXECUTED.THREAD: 4.0

Experiment 35 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VPEXTRW R8D, XMM0, 2
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 79 c5 c0 02       	vpextrw r8d,xmm0,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.99
- Reference cycles: 2.02
- UOPS_EXECUTED.THREAD: 4.0

Experiment 36 (source registers initialized by an instruction of the same kind)

Instruction: VPINSRQ XMM0, XMM1, R8, 2
Chain instruction: VPMOVMSKB R8D, XMM0
Chain latency: ≥1

Code:

   0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
   6:	c5 79 d7 c0          	vpmovmskb r8d,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1;
VPINSRQ XMM1, XMM0, R8, 2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 5.0
- Reference cycles: 1.76
- UOPS_EXECUTED.THREAD: 3.0

VPINSRQ (XMM, XMM, R64, I8) - Latency

Operands

Latency operand 2 → 1: 1

Latency operand 3 → 1: ≤4

Latency operand 2 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: ≤4

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6

Experiment 7

Experiment 8

Experiment 9

Experiment 10

Experiment 11

Experiment 12

Experiment 13

Experiment 14

Experiment 15

Experiment 16

Experiment 17

Experiment 18

Experiment 19 (source registers initialized by an instruction of the same kind)

Experiment 20 (source registers initialized by an instruction of the same kind)

Experiment 21 (source registers initialized by an instruction of the same kind)

Experiment 22 (source registers initialized by an instruction of the same kind)

Experiment 23 (source registers initialized by an instruction of the same kind)

Experiment 24 (source registers initialized by an instruction of the same kind)

Experiment 25 (source registers initialized by an instruction of the same kind)

Experiment 26 (source registers initialized by an instruction of the same kind)

Experiment 27 (source registers initialized by an instruction of the same kind)

Experiment 28 (source registers initialized by an instruction of the same kind)

Experiment 29 (source registers initialized by an instruction of the same kind)

Experiment 30 (source registers initialized by an instruction of the same kind)

Experiment 31 (source registers initialized by an instruction of the same kind)

Experiment 32 (source registers initialized by an instruction of the same kind)

Experiment 33 (source registers initialized by an instruction of the same kind)

Experiment 34 (source registers initialized by an instruction of the same kind)

Experiment 35 (source registers initialized by an instruction of the same kind)

Experiment 36 (source registers initialized by an instruction of the same kind)