VPINSRQ (XMM, XMM, R64, I8) - Port Usage

With blocking instructions for port '1':

Code:

   0:	44 8d 0d 80 00 00 00 	lea    r9d,[rip+0x80]        # 0x87
   7:	44 8d 15 80 00 00 00 	lea    r10d,[rip+0x80]        # 0x8e
   e:	44 8d 1d 80 00 00 00 	lea    r11d,[rip+0x80]        # 0x95
  15:	44 8d 25 80 00 00 00 	lea    r12d,[rip+0x80]        # 0x9c
  1c:	8d 1d 80 00 00 00    	lea    ebx,[rip+0x80]        # 0xa2
  22:	8d 0d 80 00 00 00    	lea    ecx,[rip+0x80]        # 0xa8
  28:	8d 15 80 00 00 00    	lea    edx,[rip+0x80]        # 0xae
  2e:	44 8d 0d 80 00 00 00 	lea    r9d,[rip+0x80]        # 0xb5
  35:	44 8d 15 80 00 00 00 	lea    r10d,[rip+0x80]        # 0xbc
  3c:	44 8d 1d 80 00 00 00 	lea    r11d,[rip+0x80]        # 0xc3
  43:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 10.07
- Reference cycles: 4.85
- UOPS_PORT_1: 10.02

With blocking instructions for port '5':

Code:

   0:	41 0f 6e c1          	movd   mm0,r9d
   4:	41 0f 6e c9          	movd   mm1,r9d
   8:	41 0f 6e d1          	movd   mm2,r9d
   c:	41 0f 6e d9          	movd   mm3,r9d
  10:	41 0f 6e e1          	movd   mm4,r9d
  14:	41 0f 6e e9          	movd   mm5,r9d
  18:	41 0f 6e f1          	movd   mm6,r9d
  1c:	41 0f 6e f9          	movd   mm7,r9d
  20:	41 0f 6e c1          	movd   mm0,r9d
  24:	41 0f 6e c9          	movd   mm1,r9d
  28:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.11
- Reference cycles: 5.2
- UOPS_PORT_5: 10.99

⇨ One μop that can only use port '5'

With blocking instructions for ports {'0', '1'}:

Code:

   0:	c5 e1 58 d4          	vaddpd xmm2,xmm3,xmm4
   4:	c5 e1 58 ec          	vaddpd xmm5,xmm3,xmm4
   8:	c5 e1 58 f4          	vaddpd xmm6,xmm3,xmm4
   c:	c5 e1 58 fc          	vaddpd xmm7,xmm3,xmm4
  10:	c5 61 58 c4          	vaddpd xmm8,xmm3,xmm4
  14:	c5 61 58 cc          	vaddpd xmm9,xmm3,xmm4
  18:	c5 61 58 d4          	vaddpd xmm10,xmm3,xmm4
  1c:	c5 61 58 dc          	vaddpd xmm11,xmm3,xmm4
  20:	c5 61 58 e4          	vaddpd xmm12,xmm3,xmm4
  24:	c5 e1 58 d4          	vaddpd xmm2,xmm3,xmm4
  28:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM3, [R14];
VMOVUPD XMM4, [R14];
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.16
- Reference cycles: 2.6
- UOPS_PORT_0: 4.99
- UOPS_PORT_1: 5.02

With blocking instructions for ports {'1', '5'}:

Code:

   0:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
   4:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
   8:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
   c:	47 8d 24 6e          	lea    r12d,[r14+r13*2]
  10:	43 8d 1c 6e          	lea    ebx,[r14+r13*2]
  14:	43 8d 0c 6e          	lea    ecx,[r14+r13*2]
  18:	43 8d 14 6e          	lea    edx,[r14+r13*2]
  1c:	47 8d 0c 6e          	lea    r9d,[r14+r13*2]
  20:	47 8d 14 6e          	lea    r10d,[r14+r13*2]
  24:	47 8d 1c 6e          	lea    r11d,[r14+r13*2]
  28:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS XMM1, XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 6.11
- Reference cycles: 3.12
- UOPS_PORT_5: 6.0
- UOPS_PORT_1: 6.0

⇨ One μop that can only use ports {'1', '5'}