VPINSRQ (XMM, XMM, R64, I8) - Throughput and Uops (IACA 2.3)

With different registers for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 1.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 1.0  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm0, xmm1, r8, 0x2
Total Num Of Uops: 2

With 12 independent instructions

Throughput Analysis Report
--------------------------
Block Throughput: 12.00 Cycles       Throughput Bottleneck: Backend. Port1, Port5

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 12.0 | 0.0    0.0  | 0.0    0.0  | 0.0  | 12.0 |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm0, xmm1, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm2, xmm1, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm3, xmm1, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm4, xmm1, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm5, xmm1, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm6, xmm1, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm7, xmm1, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm8, xmm1, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm9, xmm1, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm10, xmm1, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm11, xmm1, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm12, xmm1, r8, 0x2
Total Num Of Uops: 24

With the same register for for different operands

With 1 independent instruction

Throughput Analysis Report
--------------------------
Block Throughput: 1.90 Cycles       Throughput Bottleneck: FrontEnd

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 1.0  | 0.0    0.0  | 0.0    0.0  | 0.0  | 1.0  |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm0, xmm0, r8, 0x2
Total Num Of Uops: 2

With 13 independent instructions

Throughput Analysis Report
--------------------------
Block Throughput: 13.00 Cycles       Throughput Bottleneck: Backend. Port1, Port5

Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
|  Port  |  0   -  DV  |  1   |  2   -  D   |  3   -  D   |  4   |  5   |
-------------------------------------------------------------------------
| Cycles | 0.0    0.0  | 13.0 | 0.0    0.0  | 0.0    0.0  | 0.0  | 13.0 |
-------------------------------------------------------------------------


| Num Of |              Ports pressure in cycles               |    |
|  Uops  |  0  - DV  |  1  |  2  -  D  |  3  -  D  |  4  |  5  |    |
---------------------------------------------------------------------
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm0, xmm0, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm1, xmm1, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm2, xmm2, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm3, xmm3, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm4, xmm4, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm5, xmm5, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm6, xmm6, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm7, xmm7, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm8, xmm8, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm9, xmm9, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm10, xmm10, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm11, xmm11, r8, 0x2
|   2    |           | 1.0 |           |           |     | 1.0 | CP | vpinsrq xmm12, xmm12, r8, 0x2
Total Num Of Uops: 26