VPINSRQ (XMM, XMM, R64, I8) - Latency

Experiment 1

• Instruction: VPINSRQ XMM1, XMM0, R8, 2
• Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
• Chain latency: 5
• Code:

     0:	c4 c3 f9 22 c8 02    	vpinsrq xmm1,xmm0,r8,0x2
     6:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
     b:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
    10:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
    15:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
    1a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 6.0
  • Reference cycles: 6.61
  • UOPS_EXECUTED.THREAD: 7.0

Experiment 2

• Instruction: VPINSRQ XMM1, XMM0, R8, 2
• Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
• Chain latency: 5
• Code:

     0:	c4 c3 f9 22 c8 02    	vpinsrq xmm1,xmm0,r8,0x2
     6:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
     a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
     e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
    12:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
    16:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 6.0
  • Reference cycles: 6.61
  • UOPS_EXECUTED.THREAD: 7.0

Experiment 3 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM1, XMM0, R8, 2
• Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
• Chain latency: 5
• Code:

     0:	c4 c3 f9 22 c8 02    	vpinsrq xmm1,xmm0,r8,0x2
     6:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
     b:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
    10:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
    15:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
    1a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0;
  VPINSRQ XMM0, XMM1, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 6.0
  • Reference cycles: 6.61
  • UOPS_EXECUTED.THREAD: 7.0

Experiment 4 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM1, XMM0, R8, 2
• Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
• Chain latency: 5
• Code:

     0:	c4 c3 f9 22 c8 02    	vpinsrq xmm1,xmm0,r8,0x2
     6:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
     a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
     e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
    12:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
    16:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM0, XMM0, XMM0;
  VPINSRQ XMM0, XMM1, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 6.0
  • Reference cycles: 6.61
  • UOPS_EXECUTED.THREAD: 7.0

Experiment 1

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTSD2SI R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 7b 2d c0          	vcvtsd2si r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 7.73
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 2

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTSD2SI R8, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 61 fb 2d c0       	vcvtsd2si r8,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 7.73
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 3

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTSS2SI R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 7a 2d c0          	vcvtss2si r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 7.68
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 4

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTSS2SI R8, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 61 fa 2d c0       	vcvtss2si r8,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 7.79
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 5

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTTSD2SI R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 7b 2c c0          	vcvttsd2si r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 7.79
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 6

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTTSD2SI R8, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 61 fb 2c c0       	vcvttsd2si r8,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 7.68
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 7

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTTSS2SI R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 7a 2c c0          	vcvttss2si r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 7.84
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 8

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTTSS2SI R8, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 61 fa 2c c0       	vcvttss2si r8,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 6.83
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 9

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VEXTRACTPS R8D, XMM0, 2
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 c3 79 17 c0 02    	vextractps r8d,xmm0,0x2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 3.89
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 10

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VMOVD R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 c1 79 7e c0       	vmovd  r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.0
  • Reference cycles: 2.99
  • UOPS_EXECUTED.THREAD: 3.0

Experiment 11

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VMOVMSKPD R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 79 50 c0          	vmovmskpd r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 3.95
  • UOPS_EXECUTED.THREAD: 3.0

Experiment 12

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VMOVMSKPS R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 78 50 c0          	vmovmskps r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 3.95
  • UOPS_EXECUTED.THREAD: 3.0

Experiment 13

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VMOVQ R8, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 c1 f9 7e c0       	vmovq  r8,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.0
  • Reference cycles: 3.04
  • UOPS_EXECUTED.THREAD: 3.0

Experiment 14

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VPEXTRB R8D, XMM0, 2
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 c3 79 14 c0 02    	vpextrb r8d,xmm0,0x2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 3.95
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 15

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VPEXTRD R8D, XMM0, 2
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 c3 79 16 c0 02    	vpextrd r8d,xmm0,0x2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 3.89
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 16

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VPEXTRQ R8, XMM0, 2
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 c3 f9 16 c0 02    	vpextrq r8,xmm0,0x2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 3.73
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 17

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VPEXTRW R8D, XMM0, 2
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 79 c5 c0 02       	vpextrw r8d,xmm0,0x2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 3.73
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 18

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VPMOVMSKB R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 79 d7 c0          	vpmovmskb r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 3.95
  • UOPS_EXECUTED.THREAD: 3.0

Experiment 19 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTSD2SI R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 7b 2d c0          	vcvtsd2si r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 6.83
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 20 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTSD2SI R8, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 61 fb 2d c0       	vcvtsd2si r8,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 6.83
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 21 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTSS2SI R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 7a 2d c0          	vcvtss2si r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 6.83
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 22 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTSS2SI R8, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 61 fa 2d c0       	vcvtss2si r8,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 6.88
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 23 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTTSD2SI R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 7b 2c c0          	vcvttsd2si r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 6.83
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 24 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTTSD2SI R8, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 61 fb 2c c0       	vcvttsd2si r8,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 6.88
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 25 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTTSS2SI R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 7a 2c c0          	vcvttss2si r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 6.77
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 26 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VCVTTSS2SI R8, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 61 fa 2c c0       	vcvttss2si r8,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 7.0
  • Reference cycles: 7.68
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 27 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VEXTRACTPS R8D, XMM0, 2
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 c3 79 17 c0 02    	vextractps r8d,xmm0,0x2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 4.37
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 28 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VMOVD R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 c1 79 7e c0       	vmovd  r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.0
  • Reference cycles: 3.31
  • UOPS_EXECUTED.THREAD: 3.0

Experiment 29 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VMOVMSKPD R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 79 50 c0          	vmovmskpd r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 4.48
  • UOPS_EXECUTED.THREAD: 3.0

Experiment 30 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VMOVMSKPS R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 78 50 c0          	vmovmskps r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 4.37
  • UOPS_EXECUTED.THREAD: 3.0

Experiment 31 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VMOVQ R8, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 c1 f9 7e c0       	vmovq  r8,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 3.0
  • Reference cycles: 3.41
  • UOPS_EXECUTED.THREAD: 3.0

Experiment 32 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VPEXTRB R8D, XMM0, 2
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 c3 79 14 c0 02    	vpextrb r8d,xmm0,0x2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 4.32
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 33 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VPEXTRD R8D, XMM0, 2
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 c3 79 16 c0 02    	vpextrd r8d,xmm0,0x2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 4.48
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 34 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VPEXTRQ R8, XMM0, 2
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c4 c3 f9 16 c0 02    	vpextrq r8,xmm0,0x2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 4.48
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 35 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VPEXTRW R8D, XMM0, 2
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 79 c5 c0 02       	vpextrw r8d,xmm0,0x2
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 4.37
  • UOPS_EXECUTED.THREAD: 4.0

Experiment 36 (source registers initialized by an instruction of the same kind)

• Instruction: VPINSRQ XMM0, XMM1, R8, 2
• Chain instruction: VPMOVMSKB R8D, XMM0
• Chain latency: ≥1
• Code:

     0:	c4 c3 f1 22 c0 02    	vpinsrq xmm0,xmm1,r8,0x2
     6:	c5 79 d7 c0          	vpmovmskb r8d,xmm0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS XMM1, XMM1, XMM1;
  VPINSRQ XMM1, XMM0, R8, 2

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 4.0
  • Reference cycles: 4.48
  • UOPS_EXECUTED.THREAD: 3.0