XCHG (M32, R32)

Operands

• Operand 1 (r/w): Memory
• Operand 2 (r/w): Register (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D)

Available performance data

• Arrow Lake-P
• Arrow Lake-E
• Meteor Lake-P
• Meteor Lake-E
• Emerald Rapids
• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• Ivy Bridge
• Sandy Bridge
• Westmere
• Nehalem
• Wolfdale
• Conroe
• Tremont
• Goldmont Plus
• Goldmont
• Airmont
• Bonnell
• AMD Zen 5
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Arrow Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤43
  • Latency operand 1 → 1 (address, index register): ≤43
  • Latency operand 1 → 1 (memory): 20
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤20
  • Latency operand 2 → 1: ≤32
  • Latency operand 2 → 2: 13
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 20.00
  • Measured (unrolled): 20.00
• Number of μops
  • Executed: 5
  • Retire slots: 7
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 7
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*ALU+1*JMP+1*LD+1*STA+1*STD

Arrow Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 10
  • Latency operand 1 → 2 (address, base register): 14
  • Latency operand 1 → 2 (address, index register): 14
  • Latency operand 1 → 2 (memory): ≤14
  • Latency operand 2 → 1: ≤5
  • Latency operand 2 → 2: 12
• Throughput
  • Measured (loop): 15.03
  • Measured (unrolled): 15.03
• Number of μops
  • Executed: 4
  • Microcode Sequencer (MS): 4
  • Requires the complex decoder

Meteor Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤41
  • Latency operand 1 → 1 (address, index register): ≤41
  • Latency operand 1 → 1 (memory): 17
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤19
  • Latency operand 2 → 1: ≤29
  • Latency operand 2 → 2: 13
• Throughput
  • Computed from the port usage: 0.80
  • Measured (loop): 17.00
  • Measured (unrolled): 17.00
• Number of μops
  • Executed: 6
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p0156B+1*p06+1*p23A+1*p49+1*p78

Meteor Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 14
  • Latency operand 1 → 2 (address, base register): 14
  • Latency operand 1 → 2 (address, index register): 14
  • Latency operand 1 → 2 (memory): ≤14
  • Latency operand 2 → 1: ≤5
  • Latency operand 2 → 2: 12
• Throughput
  • Measured (loop): 18.00
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 5
  • Microcode Sequencer (MS): 4
  • Requires the complex decoder

Emerald Rapids

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤39
  • Latency operand 1 → 1 (address, index register): ≤39
  • Latency operand 1 → 1 (memory): 17
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤18
  • Latency operand 2 → 1: ≤29
  • Latency operand 2 → 2: 13
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 17.00
  • Measured (unrolled): 17.02
• Number of μops
  • Executed: 6
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 4*p0156B+1*p06+1*p23A+1*p49+1*p78

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤39
  • Latency operand 1 → 1 (address, index register): ≤39
  • Latency operand 1 → 1 (memory): 17
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤18
  • Latency operand 2 → 1: ≤29
  • Latency operand 2 → 2: 13
• Throughput
  • Computed from the port usage: 0.80 (if an indexed addressing mode is used: 1.00)
  • Measured (loop): 17.00
  • Measured (unrolled): 17.02 (if an indexed addressing mode is used: 17.00)
• Number of μops
  • Executed: 6
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p0156B+1*p06+1*p23A+1*p49+1*p78 (if an indexed addressing mode is used: 4*p0156B+1*p06+1*p23A+1*p49+1*p78)

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 15
  • Latency operand 1 → 2 (address, base register): 14
  • Latency operand 1 → 2 (address, index register): 14
  • Latency operand 1 → 2 (memory): ≤14
  • Latency operand 2 → 1: ≤6
  • Latency operand 2 → 2: 12
• Throughput
  • Measured (loop): 18.00
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 5
  • Microcode Sequencer (MS): 4
  • Requires the complex decoder

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤32
  • Latency operand 1 → 1 (address, index register): ≤32
  • Latency operand 1 → 1 (memory): 20
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤20
  • Latency operand 2 → 1: ≤32
  • Latency operand 2 → 2: 13
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 18.00
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 6
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p0156+1*p06+1*p23+1*p49+1*p78

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤32
  • Latency operand 1 → 1 (address, index register): ≤32
  • Latency operand 1 → 1 (memory): 20
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤20
  • Latency operand 2 → 1: ≤32
  • Latency operand 2 → 2: 13
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 18.00
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 6
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 4*p0156+1*p23+1*p49+1*p78

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤32
  • Latency operand 1 → 1 (address, index register): ≤32
  • Latency operand 1 → 1 (memory): 20
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤20
  • Latency operand 2 → 1: ≤32
  • Latency operand 2 → 2: 13
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 18.00
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 6
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 4*p0156+1*p23+1*p49+1*p78 (if an indexed addressing mode is used: 3*p0156+1*p06+1*p23+1*p49+1*p78)

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤29
  • Latency operand 1 → 1 (address, index register): ≤29
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤15
  • Latency operand 2 → 1: ≤28
  • Latency operand 2 → 2: 12
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 18.00
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 7
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0156+2*p06+2*p23+1*p4

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤29
  • Latency operand 1 → 1 (address, index register): ≤29
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤15
  • Latency operand 2 → 1: ≤28
  • Latency operand 2 → 2: 12
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 18.00
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 6
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p0156+1*p06+2*p23+1*p4

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤29
  • Latency operand 1 → 1 (address, index register): ≤29
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤15
  • Latency operand 2 → 1: ≤28
  • Latency operand 2 → 2: 12
• Throughput
  • Computed from the port usage: 1.25
  • Measured (loop): 18.00
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 7
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p0156+2*p06+2*p23+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.25
  • IACA: 1.75
• Number of μops: 8
• Port usage: 3*p0156+2*p06+1*p23+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.25
  • IACA: 1.49
• Number of μops: 8
• Port usage: 3*p0156+2*p06+1*p23+1*p237+1*p4

Coffee Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤29
  • Latency operand 1 → 1 (address, index register): ≤29
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤15
  • Latency operand 2 → 1: ≤28
  • Latency operand 2 → 2: 12
• Throughput
  • Computed from the port usage: 1.25
  • Measured (loop): 18.00
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 7
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p0156+2*p06+2*p23+1*p4

Kaby Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤29
  • Latency operand 1 → 1 (address, index register): ≤29
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤15
  • Latency operand 2 → 1: ≤28
  • Latency operand 2 → 2: 12
• Throughput
  • Computed from the port usage: 1.25
  • Measured (loop): 18.00
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 7
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p0156+2*p06+2*p23+1*p4

Skylake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤29
  • Latency operand 1 → 1 (address, index register): ≤29
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤15
  • Latency operand 2 → 1: ≤28
  • Latency operand 2 → 2: 12
• Throughput
  • Computed from the port usage: 1.25
  • Measured (loop): 18.00
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 7
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p0156+2*p06+2*p23+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.25
  • IACA: 1.75
• Number of μops: 8
• Port usage: 3*p0156+2*p06+1*p23+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.25
  • IACA: 1.49
• Number of μops: 8
• Port usage: 3*p0156+2*p06+1*p23+1*p237+1*p4

Broadwell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤32
  • Latency operand 1 → 1 (address, index register): ≤32
  • Latency operand 1 → 1 (memory): 21
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤17
  • Latency operand 2 → 1: ≤31
  • Latency operand 2 → 2: 12
• Throughput
  • Computed from the port usage: 1.25
  • Measured (loop): 21.00
  • Measured (unrolled): 21.00
• Number of μops
  • Executed: 7
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p0156+2*p06+2*p23+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.25 (with the -no_interiteration flag: 1.67)
• Number of μops: 6
• Port usage: 3*p0156+1*p23+1*p237+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.25
• Number of μops: 6
• Port usage: 3*p0156+1*p23+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.10
• Number of μops: 6
• Port usage: 3*p0156+1*p23+1*p237+1*p4

Haswell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤30
  • Latency operand 1 → 1 (address, index register): ≤30
  • Latency operand 1 → 1 (memory): 19
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤15
  • Latency operand 2 → 1: ≤29
  • Latency operand 2 → 2: 12
• Throughput
  • Computed from the port usage: 1.25
  • Measured (loop): 19.00
  • Measured (unrolled): 19.00
• Number of μops
  • Executed: 7
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p0156+2*p06+2*p23+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.25 (with the -no_interiteration flag: 1.48)
• Number of μops: 6
• Port usage: 3*p0156+1*p23+1*p237+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.25
• Number of μops: 6
• Port usage: 3*p0156+1*p23+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 6
• Port usage: 3*p0156+1*p23+1*p237+1*p4

Ivy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤33
  • Latency operand 1 → 1 (address, index register): ≤33
  • Latency operand 1 → 1 (memory): 22
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤16
  • Latency operand 2 → 1: ≤32
  • Latency operand 2 → 2: 12
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 22.00
  • Measured (unrolled): 22.00
• Number of μops
  • Executed: 7
  • Retire slots: 7
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 7
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p015+2*p23+1*p4+2*p5

Sandy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤34
  • Latency operand 1 → 1 (address, index register): ≤34
  • Latency operand 1 → 1 (memory): 23
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤17
  • Latency operand 2 → 1: ≤33
  • Latency operand 2 → 2: 12
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 23.00
  • Measured (unrolled): 23.00
• Number of μops
  • Executed: 8
  • Retire slots: 8
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p015+1*p1+2*p23+1*p4+2*p5

Westmere

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤28
  • Latency operand 1 → 1 (address, index register): ≤28
  • Latency operand 1 → 1 (memory): 19
  • Latency operand 1 → 2 (address, base register): 11
  • Latency operand 1 → 2 (address, index register): 11
  • Latency operand 1 → 2 (memory): ≤15
  • Latency operand 2 → 1: ≤27
  • Latency operand 2 → 2: 10
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 19.00
  • Measured (unrolled): 19.00
• Number of μops
  • Executed: 5
  • Retire slots: 5
  • Microcode Sequencer (MS): 16
  • Requires the complex decoder
• Port usage: 2*p015+1*p2+1*p3+1*p4
• IACA 2.1
• Latency: 5
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p2+1*p3+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p2+1*p3+1*p4

Nehalem

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤28
  • Latency operand 1 → 1 (address, index register): ≤28
  • Latency operand 1 → 1 (memory): 20
  • Latency operand 1 → 2 (address, base register): 11
  • Latency operand 1 → 2 (address, index register): 11
  • Latency operand 1 → 2 (memory): ≤16
  • Latency operand 2 → 1: ≤27
  • Latency operand 2 → 2: 10
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 20.00
  • Measured (unrolled): 20.00
• Number of μops
  • Executed: 5
  • Retire slots: 5
  • Microcode Sequencer (MS): 16
  • Requires the complex decoder
• Port usage: 2*p015+1*p2+1*p3+1*p4
• IACA 2.1
• Latency: 5
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p2+1*p3+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p2+1*p3+1*p4

Wolfdale

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤28
  • Latency operand 1 → 1 (address, index register): ≤28
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 2 (address, base register): 12
  • Latency operand 1 → 2 (address, index register): 12
  • Latency operand 1 → 2 (memory): ≤13
  • Latency operand 2 → 1: ≤27
  • Latency operand 2 → 2: 12
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 18.25
  • Measured (unrolled): 18.25
• Number of μops
  • Executed: 7
• Port usage: 1*p015+1*p2+2*p3+1*p4+1*p5

Conroe

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤28
  • Latency operand 1 → 1 (address, index register): ≤28
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 2 (address, base register): 12
  • Latency operand 1 → 2 (address, index register): 12
  • Latency operand 1 → 2 (memory): ≤13
  • Latency operand 2 → 1: ≤27
  • Latency operand 2 → 2: 12
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 18.25
  • Measured (unrolled): 18.25
• Number of μops
  • Executed: 7
• Port usage: 1*p015+1*p05+1*p2+2*p3+1*p4

Tremont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤23
  • Latency operand 1 → 1 (address, index register): ≤23
  • Latency operand 1 → 1 (memory): 7
  • Latency operand 1 → 2 (address, base register): 13
  • Latency operand 1 → 2 (address, index register): 13
  • Latency operand 1 → 2 (memory): ≤12
  • Latency operand 2 → 1: ≤3
  • Latency operand 2 → 2: 12
• Throughput
  • Measured (loop): 16.04
  • Measured (unrolled): 16.02
• Number of μops
  • Executed: 5
  • Microcode Sequencer (MS): 4
  • Requires the complex decoder

Goldmont Plus

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤3
  • Latency operand 1 → 1 (address, index register): ≤3
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 2 (address, base register): 12
  • Latency operand 1 → 2 (address, index register): 12
  • Latency operand 1 → 2 (memory): ≤11
  • Latency operand 2 → 1: ≤4
  • Latency operand 2 → 2: 10
• Throughput
  • Measured (loop): 14.00
  • Measured (unrolled): 14.00
• Number of μops
  • Executed: 3
  • Microcode Sequencer (MS): 3
  • Requires the complex decoder

Goldmont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤4
  • Latency operand 1 → 1 (address, index register): ≤4
  • Latency operand 1 → 1 (memory): 3
  • Latency operand 1 → 2 (address, base register): 12
  • Latency operand 1 → 2 (address, index register): 12
  • Latency operand 1 → 2 (memory): ≤11
  • Latency operand 2 → 1: ≤5
  • Latency operand 2 → 2: 10
• Throughput
  • Measured (loop): 13.00
  • Measured (unrolled): 13.00
• Number of μops
  • Executed: 3
  • Microcode Sequencer (MS): 3
  • Requires the complex decoder

Airmont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 2 (address, base register): 10
  • Latency operand 1 → 2 (address, index register): 10
  • Latency operand 1 → 2 (memory): ≤7
  • Latency operand 2 → 1: ≤8
  • Latency operand 2 → 2: 7
• Throughput
  • Measured (loop): 11.17
  • Measured (unrolled): 10.33
• Number of μops
  • Executed: 3
  • Microcode Sequencer (MS): 3
  • Requires the complex decoder

Bonnell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤5
  • Latency operand 1 → 1 (address, index register): ≤5
  • Latency operand 1 → 1 (memory): 9
  • Latency operand 1 → 2 (address, base register): 6
  • Latency operand 1 → 2 (address, index register): 6
  • Latency operand 1 → 2 (memory): ≤10
  • Latency operand 2 → 1: ≤3
  • Latency operand 2 → 2: 3
• Throughput
  • Measured (loop): 6.00
  • Measured (unrolled): 6.00
• Number of μops
  • Executed: 4
  • Microcode Sequencer (MS): 4
  • Requires the complex decoder

AMD Zen 5

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 11
  • Latency operand 1 → 2 (address, base register): 16
  • Latency operand 1 → 2 (address, index register): 16
  • Latency operand 1 → 2 (memory): ≤20
  • Latency operand 2 → 1: ≤7
  • Latency operand 2 → 2: 16
• Throughput
  • Measured (loop): 20.00
  • Measured (unrolled): 20.00
• Number of μops
  • Executed: 2

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 1
  • Latency operand 1 → 2 (address, base register): 5
  • Latency operand 1 → 2 (address, index register): 5
  • Latency operand 1 → 2 (memory): ≤7
  • Latency operand 2 → 1: ≤7
  • Latency operand 2 → 2: 0
• Throughput
  • Measured (loop): 7.50
  • Measured (unrolled): 7.94
• Number of μops
  • Executed: 2
• Documentation
• Throughput: 0.33
• Number of μops: 2

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 0
  • Latency operand 1 → 2 (address, base register): 5
  • Latency operand 1 → 2 (address, index register): 5
  • Latency operand 1 → 2 (memory): ≤6
  • Latency operand 2 → 1: ≤6
  • Latency operand 2 → 2: 0
• Throughput
  • Measured (loop): 7.50
  • Measured (unrolled): 7.50
• Number of μops
  • Executed: 2

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤9
  • Latency operand 1 → 1 (address, index register): ≤9
  • Latency operand 1 → 1 (memory): 7
  • Latency operand 1 → 2 (address, base register): 4
  • Latency operand 1 → 2 (address, index register): 4
  • Latency operand 1 → 2 (memory): ≤7
  • Latency operand 2 → 1: ≤7
  • Latency operand 2 → 2: 0
• Throughput
  • Measured (loop): 17.67
  • Measured (unrolled): 17.67
• Number of μops
  • Executed: 2

AMD Zen+

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤8
  • Latency operand 1 → 1 (address, index register): ≤8
  • Latency operand 1 → 1 (memory): 11
  • Latency operand 1 → 2 (address, base register): 4
  • Latency operand 1 → 2 (address, index register): 4
  • Latency operand 1 → 2 (memory): ≤6
  • Latency operand 2 → 1: ≤6
  • Latency operand 2 → 2: 0
• Throughput
  • Measured (loop): 29.37
  • Measured (unrolled): 29.38
• Number of μops
  • Executed: 2