XCHG (M32, R32)

With unroll_count=500 and no inner loop

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 19.0
- Reference cycles: 16.9
- UOPS_EXECUTED.CORE: 7.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 0.0
- UOPS_MS: 8.0
- UOPS_PORT_0: 0.39
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 1.08
- UOPS_PORT_3: 0.92
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.76
- UOPS_PORT_6: 2.35
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 19.01
- Reference cycles: 16.9
- UOPS_EXECUTED.CORE: 7.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 1.0
- UOPS_MS: 8.0
- UOPS_PORT_0: 0.47
- UOPS_PORT_1: 0.44
- UOPS_PORT_2: 0.98
- UOPS_PORT_3: 1.02
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.46
- UOPS_PORT_6: 2.63
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 19.0
- Reference cycles: 16.89
- UOPS_EXECUTED.CORE: 7.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.1
- UOPS_MS: 8.01
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.48
- UOPS_PORT_2: 1.02
- UOPS_PORT_3: 0.98
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.55
- UOPS_PORT_6: 2.57
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.1

With loop_count=100 and unroll_count=100

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 19.0
- Reference cycles: 16.89
- UOPS_EXECUTED.CORE: 7.01
- RETIRE_SLOTS: 8.01
- UOPS_MITE: 0.01
- UOPS_MS: 8.01
- UOPS_PORT_0: 0.46
- UOPS_PORT_1: 0.55
- UOPS_PORT_2: 1.08
- UOPS_PORT_3: 0.92
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.54
- UOPS_PORT_6: 2.46
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	45 87 4e 04          	xchg   DWORD PTR [r14+0x4],r9d
   7:	45 87 56 08          	xchg   DWORD PTR [r14+0x8],r10d
   b:	45 87 5e 0c          	xchg   DWORD PTR [r14+0xc],r11d

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 91.99
- Reference cycles: 81.76
- UOPS_EXECUTED.CORE: 28.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 0.0
- UOPS_MS: 32.0
- UOPS_PORT_0: 4.04
- UOPS_PORT_1: 4.55
- UOPS_PORT_2: 4.34
- UOPS_PORT_3: 3.67
- UOPS_PORT_4: 11.94
- UOPS_PORT_5: 5.2
- UOPS_PORT_6: 10.2
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=2

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	45 87 4e 04          	xchg   DWORD PTR [r14+0x4],r9d
   7:	45 87 56 08          	xchg   DWORD PTR [r14+0x8],r10d
   b:	45 87 5e 0c          	xchg   DWORD PTR [r14+0xc],r11d

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 92.5
- Reference cycles: 82.22
- UOPS_EXECUTED.CORE: 28.5
- RETIRE_SLOTS: 32.5
- UOPS_MITE: 0.5
- UOPS_MS: 32.03
- UOPS_PORT_0: 3.89
- UOPS_PORT_1: 4.22
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 3.99
- UOPS_PORT_4: 11.99
- UOPS_PORT_5: 4.52
- UOPS_PORT_6: 11.87
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With loop_count=100 and unroll_count=20

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	45 87 4e 04          	xchg   DWORD PTR [r14+0x4],r9d
   7:	45 87 56 08          	xchg   DWORD PTR [r14+0x8],r10d
   b:	45 87 5e 0c          	xchg   DWORD PTR [r14+0xc],r11d

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 92.05
- Reference cycles: 81.82
- UOPS_EXECUTED.CORE: 28.05
- RETIRE_SLOTS: 32.05
- UOPS_MITE: 0.05
- UOPS_MS: 32.03
- UOPS_PORT_0: 3.99
- UOPS_PORT_1: 4.26
- UOPS_PORT_2: 4.37
- UOPS_PORT_3: 3.63
- UOPS_PORT_4: 11.99
- UOPS_PORT_5: 4.25
- UOPS_PORT_6: 11.51
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	45 87 4e 04          	xchg   DWORD PTR [r14+0x4],r9d
   7:	45 87 56 08          	xchg   DWORD PTR [r14+0x8],r10d
   b:	45 87 5e 0c          	xchg   DWORD PTR [r14+0xc],r11d
   f:	45 87 66 10          	xchg   DWORD PTR [r14+0x10],r12d
  13:	41 87 5e 14          	xchg   DWORD PTR [r14+0x14],ebx
  17:	41 87 4e 18          	xchg   DWORD PTR [r14+0x18],ecx
  1b:	41 87 56 1c          	xchg   DWORD PTR [r14+0x1c],edx

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 183.98
- Reference cycles: 163.52
- UOPS_EXECUTED.CORE: 56.0
- RETIRE_SLOTS: 64.0
- UOPS_MITE: 0.0
- UOPS_MS: 64.0
- UOPS_PORT_0: 8.14
- UOPS_PORT_1: 8.8
- UOPS_PORT_2: 8.63
- UOPS_PORT_3: 7.35
- UOPS_PORT_4: 23.73
- UOPS_PORT_5: 10.74
- UOPS_PORT_6: 20.28
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=1

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	45 87 4e 04          	xchg   DWORD PTR [r14+0x4],r9d
   7:	45 87 56 08          	xchg   DWORD PTR [r14+0x8],r10d
   b:	45 87 5e 0c          	xchg   DWORD PTR [r14+0xc],r11d
   f:	45 87 66 10          	xchg   DWORD PTR [r14+0x10],r12d
  13:	41 87 5e 14          	xchg   DWORD PTR [r14+0x14],ebx
  17:	41 87 4e 18          	xchg   DWORD PTR [r14+0x18],ecx
  1b:	41 87 56 1c          	xchg   DWORD PTR [r14+0x1c],edx

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 185.0
- Reference cycles: 164.45
- UOPS_EXECUTED.CORE: 57.01
- RETIRE_SLOTS: 65.0
- UOPS_MITE: 1.0
- UOPS_MS: 64.06
- UOPS_PORT_0: 7.76
- UOPS_PORT_1: 8.23
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 23.97
- UOPS_PORT_5: 8.96
- UOPS_PORT_6: 24.06
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=10

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	45 87 4e 04          	xchg   DWORD PTR [r14+0x4],r9d
   7:	45 87 56 08          	xchg   DWORD PTR [r14+0x8],r10d
   b:	45 87 5e 0c          	xchg   DWORD PTR [r14+0xc],r11d
   f:	45 87 66 10          	xchg   DWORD PTR [r14+0x10],r12d
  13:	41 87 5e 14          	xchg   DWORD PTR [r14+0x14],ebx
  17:	41 87 4e 18          	xchg   DWORD PTR [r14+0x18],ecx
  1b:	41 87 56 1c          	xchg   DWORD PTR [r14+0x1c],edx

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 184.1
- Reference cycles: 163.65
- UOPS_EXECUTED.CORE: 56.1
- RETIRE_SLOTS: 64.1
- UOPS_MITE: 0.1
- UOPS_MS: 64.06
- UOPS_PORT_0: 8.02
- UOPS_PORT_1: 8.56
- UOPS_PORT_2: 8.75
- UOPS_PORT_3: 7.25
- UOPS_PORT_4: 23.97
- UOPS_PORT_5: 8.47
- UOPS_PORT_6: 23.04
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.1

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 19.0
- Reference cycles: 16.9
- UOPS_EXECUTED.CORE: 7.0
- RETIRE_SLOTS: 8.0
- UOPS_MITE: 0.0
- UOPS_MS: 8.0
- UOPS_PORT_0: 0.4
- UOPS_PORT_1: 0.5
- UOPS_PORT_2: 1.08
- UOPS_PORT_3: 0.92
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.78
- UOPS_PORT_6: 2.33
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d
   4:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 19.01
- Reference cycles: 16.9
- UOPS_EXECUTED.CORE: 7.0
- RETIRE_SLOTS: 9.0
- UOPS_MITE: 1.0
- UOPS_MS: 8.0
- UOPS_PORT_0: 0.47
- UOPS_PORT_1: 0.45
- UOPS_PORT_2: 0.97
- UOPS_PORT_3: 1.03
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.46
- UOPS_PORT_6: 2.63
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000 and unroll_count=10

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 19.0
- Reference cycles: 16.89
- UOPS_EXECUTED.CORE: 7.1
- RETIRE_SLOTS: 8.1
- UOPS_MITE: 0.1
- UOPS_MS: 8.01
- UOPS_PORT_0: 0.5
- UOPS_PORT_1: 0.48
- UOPS_PORT_2: 1.04
- UOPS_PORT_3: 0.96
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.55
- UOPS_PORT_6: 2.58
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.1

With loop_count=100 and unroll_count=100

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 19.0
- Reference cycles: 16.89
- UOPS_EXECUTED.CORE: 7.01
- RETIRE_SLOTS: 8.01
- UOPS_MITE: 0.01
- UOPS_MS: 8.01
- UOPS_PORT_0: 0.46
- UOPS_PORT_1: 0.55
- UOPS_PORT_2: 1.08
- UOPS_PORT_3: 0.92
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.54
- UOPS_PORT_6: 2.47
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d
   4:	47 87 4c 2e 04       	xchg   DWORD PTR [r14+r13*1+0x4],r9d
   9:	47 87 54 2e 08       	xchg   DWORD PTR [r14+r13*1+0x8],r10d
   e:	47 87 5c 2e 0c       	xchg   DWORD PTR [r14+r13*1+0xc],r11d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 92.0
- Reference cycles: 81.76
- UOPS_EXECUTED.CORE: 28.0
- RETIRE_SLOTS: 32.0
- UOPS_MITE: 0.0
- UOPS_MS: 32.0
- UOPS_PORT_0: 4.02
- UOPS_PORT_1: 4.57
- UOPS_PORT_2: 4.29
- UOPS_PORT_3: 3.72
- UOPS_PORT_4: 12.0
- UOPS_PORT_5: 5.3
- UOPS_PORT_6: 10.17
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=2

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d
   4:	47 87 4c 2e 04       	xchg   DWORD PTR [r14+r13*1+0x4],r9d
   9:	47 87 54 2e 08       	xchg   DWORD PTR [r14+r13*1+0x8],r10d
   e:	47 87 5c 2e 0c       	xchg   DWORD PTR [r14+r13*1+0xc],r11d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 92.5
- Reference cycles: 82.23
- UOPS_EXECUTED.CORE: 28.5
- RETIRE_SLOTS: 32.5
- UOPS_MITE: 0.5
- UOPS_MS: 32.03
- UOPS_PORT_0: 3.89
- UOPS_PORT_1: 4.23
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 3.99
- UOPS_PORT_4: 11.99
- UOPS_PORT_5: 4.51
- UOPS_PORT_6: 11.91
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.5

With loop_count=100 and unroll_count=20

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d
   4:	47 87 4c 2e 04       	xchg   DWORD PTR [r14+r13*1+0x4],r9d
   9:	47 87 54 2e 08       	xchg   DWORD PTR [r14+r13*1+0x8],r10d
   e:	47 87 5c 2e 0c       	xchg   DWORD PTR [r14+r13*1+0xc],r11d

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 92.05
- Reference cycles: 81.82
- UOPS_EXECUTED.CORE: 28.05
- RETIRE_SLOTS: 32.05
- UOPS_MITE: 0.05
- UOPS_MS: 32.03
- UOPS_PORT_0: 3.96
- UOPS_PORT_1: 4.25
- UOPS_PORT_2: 4.38
- UOPS_PORT_3: 3.62
- UOPS_PORT_4: 11.99
- UOPS_PORT_5: 4.29
- UOPS_PORT_6: 11.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.05

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d
   4:	47 87 4c 2e 04       	xchg   DWORD PTR [r14+r13*1+0x4],r9d
   9:	47 87 54 2e 08       	xchg   DWORD PTR [r14+r13*1+0x8],r10d
   e:	47 87 5c 2e 0c       	xchg   DWORD PTR [r14+r13*1+0xc],r11d
  13:	47 87 64 2e 10       	xchg   DWORD PTR [r14+r13*1+0x10],r12d
  18:	43 87 5c 2e 14       	xchg   DWORD PTR [r14+r13*1+0x14],ebx
  1d:	43 87 4c 2e 18       	xchg   DWORD PTR [r14+r13*1+0x18],ecx
  22:	43 87 54 2e 1c       	xchg   DWORD PTR [r14+r13*1+0x1c],edx

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 184.0
- Reference cycles: 168.32
- UOPS_EXECUTED.CORE: 56.0
- RETIRE_SLOTS: 64.0
- UOPS_MITE: 0.0
- UOPS_MS: 64.0
- UOPS_PORT_0: 8.15
- UOPS_PORT_1: 8.94
- UOPS_PORT_2: 8.55
- UOPS_PORT_3: 7.44
- UOPS_PORT_4: 24.0
- UOPS_PORT_5: 10.89
- UOPS_PORT_6: 20.19
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=1000 and unroll_count=1

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d
   4:	47 87 4c 2e 04       	xchg   DWORD PTR [r14+r13*1+0x4],r9d
   9:	47 87 54 2e 08       	xchg   DWORD PTR [r14+r13*1+0x8],r10d
   e:	47 87 5c 2e 0c       	xchg   DWORD PTR [r14+r13*1+0xc],r11d
  13:	47 87 64 2e 10       	xchg   DWORD PTR [r14+r13*1+0x10],r12d
  18:	43 87 5c 2e 14       	xchg   DWORD PTR [r14+r13*1+0x14],ebx
  1d:	43 87 4c 2e 18       	xchg   DWORD PTR [r14+r13*1+0x18],ecx
  22:	43 87 54 2e 1c       	xchg   DWORD PTR [r14+r13*1+0x1c],edx

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 185.0
- Reference cycles: 164.45
- UOPS_EXECUTED.CORE: 57.01
- RETIRE_SLOTS: 65.0
- UOPS_MITE: 1.0
- UOPS_MS: 64.06
- UOPS_PORT_0: 7.77
- UOPS_PORT_1: 8.23
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 23.97
- UOPS_PORT_5: 8.96
- UOPS_PORT_6: 24.04
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100 and unroll_count=10

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d
   4:	47 87 4c 2e 04       	xchg   DWORD PTR [r14+r13*1+0x4],r9d
   9:	47 87 54 2e 08       	xchg   DWORD PTR [r14+r13*1+0x8],r10d
   e:	47 87 5c 2e 0c       	xchg   DWORD PTR [r14+r13*1+0xc],r11d
  13:	47 87 64 2e 10       	xchg   DWORD PTR [r14+r13*1+0x10],r12d
  18:	43 87 5c 2e 14       	xchg   DWORD PTR [r14+r13*1+0x14],ebx
  1d:	43 87 4c 2e 18       	xchg   DWORD PTR [r14+r13*1+0x18],ecx
  22:	43 87 54 2e 1c       	xchg   DWORD PTR [r14+r13*1+0x1c],edx

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 184.1
- Reference cycles: 163.65
- UOPS_EXECUTED.CORE: 56.1
- RETIRE_SLOTS: 64.1
- UOPS_MITE: 0.1
- UOPS_MS: 64.06
- UOPS_PORT_0: 8.05
- UOPS_PORT_1: 8.48
- UOPS_PORT_2: 8.75
- UOPS_PORT_3: 7.25
- UOPS_PORT_4: 23.97
- UOPS_PORT_5: 8.51
- UOPS_PORT_6: 23.04
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.1

XCHG (M32, R32) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10