XCHG (M32, R32) - Latency


Operands


Latency operand 1 → 1 (address, base register): ≤9

Latency operand 1 → 1 (address, index register): ≤9

Latency operand 1 → 1 (memory): 7

Latency operand 1 → 2 (address, base register): 4

Latency operand 1 → 2 (address, index register): 4

Latency operand 1 → 2 (memory): ≤7

Latency operand 2 → 1: ≤7

Latency operand 2 → 2: 0


Latency operand 1 → 1 (address, base register): ≤9

Experiment 1

Experiment 2 (with additional nop)


Latency operand 1 → 1 (address, index register): ≤9

Experiment 1

Experiment 2 (with additional nop)


Latency operand 1 → 1 (memory): 7

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)


Latency operand 1 → 2 (address, base register): 4

Experiment 1


Latency operand 1 → 2 (address, index register): 4

Experiment 1


Latency operand 1 → 2 (memory): ≤7

Experiment 1


Latency operand 2 → 1: ≤7

Experiment 1


Latency operand 2 → 2: 0

Experiment 1

Experiment 2

Experiment 3 (with dependency-breaking instructions)