XCHG (M32, R32) - Latency


Operands


Latency operand 1 → 1 (address, base register): ≤10

Latency operand 1 → 1 (address, index register): ≤10

Latency operand 1 → 1 (memory): 0

Latency operand 1 → 2 (address, base register): 5

Latency operand 1 → 2 (address, index register): 5

Latency operand 1 → 2 (memory): ≤6

Latency operand 2 → 1: ≤6

Latency operand 2 → 2: 0


Latency operand 1 → 1 (address, base register): ≤10

Experiment 1

Experiment 2 (with additional nop)


Latency operand 1 → 1 (address, index register): ≤10

Experiment 1

Experiment 2 (with additional nop)


Latency operand 1 → 1 (memory): 0

Experiment 1

Experiment 2

Experiment 3 (with dependency-breaking instructions)


Latency operand 1 → 2 (address, base register): 5

Experiment 1


Latency operand 1 → 2 (address, index register): 5

Experiment 1


Latency operand 1 → 2 (memory): ≤6

Experiment 1


Latency operand 2 → 1: ≤6

Experiment 1


Latency operand 2 → 2: 0

Experiment 1

Experiment 2

Experiment 3 (with dependency-breaking instructions)