XCHG (M32, R32)

Experiment 1

Instruction: XCHG dword ptr [R14], R8D
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥17

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	4d 63 e4             	movsxd r12,r12d
  24:	4d 63 e4             	movsxd r12,r12d
  27:	4d 63 e4             	movsxd r12,r12d
  2a:	4d 63 e4             	movsxd r12,r12d
  2d:	4d 63 e4             	movsxd r12,r12d
  30:	4d 31 e6             	xor    r14,r12
  33:	4d 31 e6             	xor    r14,r12

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 26.98
- Reference cycles: 13.5
- UOPS_RETIRED.ALL: 20.0

Experiment 2 (with additional nop)

Instruction: XCHG dword ptr [R14], R8D
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥17

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	4d 63 e4             	movsxd r12,r12d
  24:	4d 63 e4             	movsxd r12,r12d
  27:	4d 63 e4             	movsxd r12,r12d
  2a:	4d 63 e4             	movsxd r12,r12d
  2d:	4d 63 e4             	movsxd r12,r12d
  30:	4d 31 e6             	xor    r14,r12
  33:	4d 31 e6             	xor    r14,r12
  36:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 19.0
- Core cycles: 26.99
- Reference cycles: 13.52
- UOPS_RETIRED.ALL: 21.0

Latency operand 1 → 1 (address, index register): ≤10

Experiment 1

Instruction: XCHG dword ptr [R14+R13], R8D
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥17

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d
   4:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	4d 63 e4             	movsxd r12,r12d
  29:	4d 63 e4             	movsxd r12,r12d
  2c:	4d 63 e4             	movsxd r12,r12d
  2f:	4d 63 e4             	movsxd r12,r12d
  32:	4d 31 e5             	xor    r13,r12
  35:	4d 31 e5             	xor    r13,r12

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 26.99
- Reference cycles: 13.5
- UOPS_RETIRED.ALL: 20.0

Experiment 2 (with additional nop)

Instruction: XCHG dword ptr [R14+R13], R8D
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥17

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d
   4:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	4d 63 e4             	movsxd r12,r12d
  29:	4d 63 e4             	movsxd r12,r12d
  2c:	4d 63 e4             	movsxd r12,r12d
  2f:	4d 63 e4             	movsxd r12,r12d
  32:	4d 31 e5             	xor    r13,r12
  35:	4d 31 e5             	xor    r13,r12
  38:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 19.0
- Core cycles: 26.99
- Reference cycles: 13.5
- UOPS_RETIRED.ALL: 21.0

Latency operand 1 → 1 (memory): 6

Experiment 1

Instruction: XCHG dword ptr [R14], R8D
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOV [R14], R12D
Chain latency: 14

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	4d 63 e4             	movsxd r12,r12d
  24:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 20.49
- Reference cycles: 10.23
- UOPS_RETIRED.ALL: 15.0

Experiment 2

Instruction: XCHG dword ptr [R14], R8D

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 10.33
- Reference cycles: 5.16
- UOPS_RETIRED.ALL: 3.0

Experiment 3 (with dependency-breaking instructions)

Instruction: XCHG dword ptr [R14], R8D
Chain instruction: MOV R8D, 0

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	41 b8 00 00 00 00    	mov    r8d,0x0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 10.33
- Reference cycles: 5.16
- UOPS_RETIRED.ALL: 4.0

Latency operand 1 → 2 (address, base register): 10

Experiment 1

Instruction: XCHG dword ptr [R14], R8D
Chain instructions: MOVSX R8, R8D;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8
Chain latency: 15

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	4d 63 c0             	movsxd r8,r8d
   6:	4d 31 c6             	xor    r14,r8
   9:	4d 31 c6             	xor    r14,r8
   c:	4d 31 c6             	xor    r14,r8
   f:	4d 31 c6             	xor    r14,r8
  12:	4d 31 c6             	xor    r14,r8
  15:	4d 31 c6             	xor    r14,r8
  18:	4d 31 c6             	xor    r14,r8
  1b:	4d 31 c6             	xor    r14,r8
  1e:	4d 31 c6             	xor    r14,r8
  21:	4d 31 c6             	xor    r14,r8
  24:	4d 31 c6             	xor    r14,r8
  27:	4d 31 c6             	xor    r14,r8
  2a:	4d 31 c6             	xor    r14,r8
  2d:	4d 31 c6             	xor    r14,r8

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 25.0
- Reference cycles: 12.48
- UOPS_RETIRED.ALL: 18.0

Latency operand 1 → 2 (address, index register): 10

Experiment 1

Instruction: XCHG dword ptr [R14+R13], R8D
Chain instructions: MOVSX R8, R8D;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8
Chain latency: 15

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d
   4:	4d 63 c0             	movsxd r8,r8d
   7:	4d 31 c5             	xor    r13,r8
   a:	4d 31 c5             	xor    r13,r8
   d:	4d 31 c5             	xor    r13,r8
  10:	4d 31 c5             	xor    r13,r8
  13:	4d 31 c5             	xor    r13,r8
  16:	4d 31 c5             	xor    r13,r8
  19:	4d 31 c5             	xor    r13,r8
  1c:	4d 31 c5             	xor    r13,r8
  1f:	4d 31 c5             	xor    r13,r8
  22:	4d 31 c5             	xor    r13,r8
  25:	4d 31 c5             	xor    r13,r8
  28:	4d 31 c5             	xor    r13,r8
  2b:	4d 31 c5             	xor    r13,r8
  2e:	4d 31 c5             	xor    r13,r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 25.0
- Reference cycles: 12.48
- UOPS_RETIRED.ALL: 18.0

Latency operand 1 → 2 (memory): ≤7

Experiment 1

Instruction: XCHG dword ptr [R14], R8D
Chain instructions: MOVSX R12, R8D;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥15

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	4d 63 e0             	movsxd r12,r8d
   6:	4d 63 e4             	movsxd r12,r12d
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	4d 63 e4             	movsxd r12,r12d
  24:	4d 63 e4             	movsxd r12,r12d
  27:	4d 63 e4             	movsxd r12,r12d
  2a:	4d 63 e4             	movsxd r12,r12d
  2d:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 22.0
- Reference cycles: 10.99
- UOPS_RETIRED.ALL: 18.0

Latency operand 2 → 1: ≤8

Experiment 1

Instruction: XCHG dword ptr [R14], R8D
Chain instructions: MOV R8D, [R14];MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: ≥15

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	45 8b 06             	mov    r8d,DWORD PTR [r14]
   6:	4d 63 c0             	movsxd r8,r8d
   9:	4d 63 c0             	movsxd r8,r8d
   c:	4d 63 c0             	movsxd r8,r8d
   f:	4d 63 c0             	movsxd r8,r8d
  12:	4d 63 c0             	movsxd r8,r8d
  15:	4d 63 c0             	movsxd r8,r8d
  18:	4d 63 c0             	movsxd r8,r8d
  1b:	4d 63 c0             	movsxd r8,r8d
  1e:	4d 63 c0             	movsxd r8,r8d
  21:	4d 63 c0             	movsxd r8,r8d
  24:	4d 63 c0             	movsxd r8,r8d
  27:	4d 63 c0             	movsxd r8,r8d
  2a:	4d 63 c0             	movsxd r8,r8d
  2d:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 23.01
- Reference cycles: 11.53
- UOPS_RETIRED.ALL: 18.0

Latency operand 2 → 2: 7

Experiment 1

Instruction: XCHG dword ptr [R14], R8D
Chain instructions: MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 15

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	4d 63 c0             	movsxd r8,r8d
   6:	4d 63 c0             	movsxd r8,r8d
   9:	4d 63 c0             	movsxd r8,r8d
   c:	4d 63 c0             	movsxd r8,r8d
   f:	4d 63 c0             	movsxd r8,r8d
  12:	4d 63 c0             	movsxd r8,r8d
  15:	4d 63 c0             	movsxd r8,r8d
  18:	4d 63 c0             	movsxd r8,r8d
  1b:	4d 63 c0             	movsxd r8,r8d
  1e:	4d 63 c0             	movsxd r8,r8d
  21:	4d 63 c0             	movsxd r8,r8d
  24:	4d 63 c0             	movsxd r8,r8d
  27:	4d 63 c0             	movsxd r8,r8d
  2a:	4d 63 c0             	movsxd r8,r8d
  2d:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 22.0
- Reference cycles: 11.01
- UOPS_RETIRED.ALL: 18.0

Experiment 2

Instruction: XCHG dword ptr [R14], R8D

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 10.56
- Reference cycles: 5.31
- UOPS_RETIRED.ALL: 3.0

Experiment 3 (with dependency-breaking instructions)

Instruction: XCHG dword ptr [R14], R8D
Chain instruction: MOV dword ptr [R14], 0

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	41 c7 06 00 00 00 00 	mov    DWORD PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 13.0
- Reference cycles: 6.52
- UOPS_RETIRED.ALL: 4.0

XCHG (M32, R32) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤10

Latency operand 1 → 1 (address, index register): ≤10

Latency operand 1 → 1 (memory): 6

Latency operand 1 → 2 (address, base register): 10

Latency operand 1 → 2 (address, index register): 10

Latency operand 1 → 2 (memory): ≤7

Latency operand 2 → 1: ≤8

Latency operand 2 → 2: 7

Latency operand 1 → 1 (address, base register): ≤10

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤10

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (memory): 6

Experiment 1

Experiment 2

Experiment 3 (with dependency-breaking instructions)

Latency operand 1 → 2 (address, base register): 10

Experiment 1

Latency operand 1 → 2 (address, index register): 10

Experiment 1

Latency operand 1 → 2 (memory): ≤7

Experiment 1

Latency operand 2 → 1: ≤8

Experiment 1

Latency operand 2 → 2: 7

Experiment 1

Experiment 2

Experiment 3 (with dependency-breaking instructions)