XCHG (M32, R32) - Port Usage

With lfence (to avoid incorrect counts due to replays)

Code:

   0:	45 87 06             	xchg   DWORD PTR [r14],r8d
   3:	90                   	nop
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop
   c:	90                   	nop
   d:	0f ae e8             	lfence

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 31.01
- Reference cycles: 21.55
- UOPS_DISPATCHED.INT_EU_ALL: 4.0
- UOPS_DISPATCHED.ALU: 3.0
- UOPS_DISPATCHED.LD: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 1.0

No uops

With an indexed addressing mode

With lfence (to avoid incorrect counts due to replays)

Code:

   0:	47 87 04 2e          	xchg   DWORD PTR [r14+r13*1],r8d
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop
   c:	90                   	nop
   d:	90                   	nop
   e:	0f ae e8             	lfence

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 31.01
- Reference cycles: 21.72
- UOPS_DISPATCHED.INT_EU_ALL: 4.0
- UOPS_DISPATCHED.ALU: 3.0
- UOPS_DISPATCHED.LD: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 1.0
- UOPS_DISPATCHED.SHIFT: 0.0
- UOPS_DISPATCHED.JMP: 1.0
- UOPS_DISPATCHED.STA: 1.0

No uops