SHLX (R64, M64, R64)

Operands

• Operand 1 (w): Register (RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, R8, R9, R10, R11, R12, R13, R14, R15)
• Operand 2 (r): Memory
• Operand 3 (r): Register (RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, R8, R9, R10, R11, R12, R13, R14, R15)

Available performance data

• Arrow Lake-P
• Arrow Lake-E
• Meteor Lake-P
• Meteor Lake-E
• Emerald Rapids
• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• AMD Zen 5
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Arrow Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤6
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.33
  • Measured (loop): 0.33
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (6 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*LD+1*SHIFT

Arrow Lake-E

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤1
  • Latency operand 3 → 1: 2
• Throughput
  • Measured (loop): 0.33
  • Measured (unrolled): 0.33
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Meteor Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤6
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23A

Meteor Lake-E

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤1
  • Latency operand 3 → 1: 2
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Emerald Rapids

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤6
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23A

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤6
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23A

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤1
  • Latency operand 3 → 1: 2
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Rocket Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤6
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23

Tiger Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤6
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23

Ice Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤6
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23

Cascade Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤3
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23

Cannon Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤3
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23

Skylake-X

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤3
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p06+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p06+1*p23

Coffee Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤3
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23

Kaby Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤3
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23

Skylake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤3
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p06+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p06+1*p23

Broadwell

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤5
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50 (with the -no_interiteration flag: 0.50)
• Number of μops: 2
• Port usage: 1*p06+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p06+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p06+1*p23

Haswell

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 6
  • Latency operand 2 → 1 (address, index register): 6
  • Latency operand 2 → 1 (memory): ≤5
  • Latency operand 3 → 1: 1
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p06+1*p23
• IACA 2.1
• Latency: 6
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50 (with the -no_interiteration flag: 0.50)
• Number of μops: 2
• Port usage: 1*p06+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50 (with the -no_interiteration flag: 0.50)
• Number of μops: 2
• Port usage: 1*p06+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p06+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p06+1*p23

AMD Zen 5

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤1
  • Latency operand 3 → 1: 1
• Throughput
  • Measured (loop): 0.33
  • Measured (unrolled): 0.33
• Number of μops
  • Executed: 1
• Documentation
• Latency: 1
• Throughput: 0.33
• Number of μops: 1

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤1
  • Latency operand 3 → 1: 1
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 2
• Documentation
• Latency: 1
• Throughput: 0.50
• Number of μops: 1
• Port usage: ALU1/2

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤7
  • Latency operand 3 → 1: 1
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 2
• Documentation
• Latency: 1
• Throughput: 0.50
• Number of μops: 1
• Port usage: ALU1/2

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤1
  • Latency operand 3 → 1: 1
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 2
• Documentation
• Latency: 1
• Throughput: 0.25
• Number of μops: 1
• Port usage: ALU

AMD Zen+

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): 5
  • Latency operand 2 → 1 (address, index register): 5
  • Latency operand 2 → 1 (memory): ≤7
  • Latency operand 3 → 1: 1
• Throughput
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 2