SHLX (R64, M64, R64)

Experiment 1

Instruction: SHLX R8, qword ptr [R14], R9
Chain instructions: MOVSX R8, R8D;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8
Chain latency: 5

Code:

   0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
   5:	4d 63 c0             	movsxd r8,r8d
   8:	4d 31 c6             	xor    r14,r8
   b:	4d 31 c6             	xor    r14,r8
   e:	4d 31 c6             	xor    r14,r8
  11:	4d 31 c6             	xor    r14,r8

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- MPERF: 7.83
- APERF: 10.0
- UOPS: 7.0

Experiment 2 (with clean upper 32 bits)

Instruction: SHLX R8, qword ptr [R14], R9
Chain instructions: MOVSX R8, R8D;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8
Chain latency: 5

Code:

   0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
   5:	4d 63 c0             	movsxd r8,r8d
   8:	4d 31 c6             	xor    r14,r8
   b:	4d 31 c6             	xor    r14,r8
   e:	4d 31 c6             	xor    r14,r8
  11:	4d 31 c6             	xor    r14,r8

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV R9D, R9D;

Show nanoBench command
Results:
- MPERF: 7.96
- APERF: 10.0
- UOPS: 7.0

Latency operand 2 → 1 (address, index register): 5

Experiment 1

Instruction: SHLX R8, qword ptr [R14+R13], R9
Chain instructions: MOVSX R8, R8D;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8
Chain latency: 5

Code:

   0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
   6:	4d 63 c0             	movsxd r8,r8d
   9:	4d 31 c5             	xor    r13,r8
   c:	4d 31 c5             	xor    r13,r8
   f:	4d 31 c5             	xor    r13,r8
  12:	4d 31 c5             	xor    r13,r8

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- MPERF: 8.26
- APERF: 10.0
- UOPS: 7.0

Experiment 2 (with clean upper 32 bits)

Instruction: SHLX R8, qword ptr [R14+R13], R9
Chain instructions: MOVSX R8, R8D;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8
Chain latency: 5

Code:

   0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
   6:	4d 63 c0             	movsxd r8,r8d
   9:	4d 31 c5             	xor    r13,r8
   c:	4d 31 c5             	xor    r13,r8
   f:	4d 31 c5             	xor    r13,r8
  12:	4d 31 c5             	xor    r13,r8

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13;
MOV R9D, R9D;

Show nanoBench command
Results:
- MPERF: 7.89
- APERF: 9.97
- UOPS: 7.0

Latency operand 2 → 1 (memory): ≤7

Experiment 1

Instruction: SHLX R8, qword ptr [R14], R9
Chain instructions: MOVSX R12, R8D;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12
Chain latency: ≥5

Code:

   0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
   5:	4d 63 e0             	movsxd r12,r8d
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 89 26             	mov    QWORD PTR [r14],r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- MPERF: 9.62
- APERF: 11.94
- UOPS: 7.0

Experiment 2 (with clean upper 32 bits)

Instruction: SHLX R8, qword ptr [R14], R9
Chain instructions: MOVSX R12, R8D;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12
Chain latency: ≥5

Code:

   0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
   5:	4d 63 e0             	movsxd r12,r8d
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 89 26             	mov    QWORD PTR [r14],r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV R9D, R9D;

Show nanoBench command
Results:
- MPERF: 9.56
- APERF: 11.94
- UOPS: 7.0

Latency operand 3 → 1: 1

Experiment 1

Instruction: SHLX R9, qword ptr [R14], R8
Chain instruction: SHLX R8, qword ptr [R14], R9

Code:

   0:	c4 42 b9 f7 0e       	shlx   r9,QWORD PTR [r14],r8
   5:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- MPERF: 1.67
- APERF: 2.0
- UOPS: 4.0

Experiment 2

Instruction: SHLX R9, qword ptr [R14], R8
Chain instructions: MOVSX R8, R9D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 5

Code:

   0:	c4 42 b9 f7 0e       	shlx   r9,QWORD PTR [r14],r8
   5:	4d 63 c1             	movsxd r8,r9d
   8:	4d 63 c0             	movsxd r8,r8d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- MPERF: 4.81
- APERF: 6.01
- UOPS: 7.0

SHLX (R64, M64, R64) - Latency

Operands

Latency operand 2 → 1 (address, base register): 5

Latency operand 2 → 1 (address, index register): 5

Latency operand 2 → 1 (memory): ≤7

Latency operand 3 → 1: 1

Latency operand 2 → 1 (address, base register): 5

Experiment 1

Experiment 2 (with clean upper 32 bits)

Latency operand 2 → 1 (address, index register): 5

Experiment 1

Experiment 2 (with clean upper 32 bits)

Latency operand 2 → 1 (memory): ≤7

Experiment 1

Experiment 2 (with clean upper 32 bits)

Latency operand 3 → 1: 1

Experiment 1

Experiment 2