SHLX (R64, M64, R64) - Port Usage

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c2 00       	rol    r10w,0x0
   5:	66 41 c1 c3 00       	rol    r11w,0x0
   a:	66 41 c1 c4 00       	rol    r12w,0x0
   f:	66 c1 c3 00          	rol    bx,0x0
  13:	66 c1 c1 00          	rol    cx,0x0
  17:	66 c1 c2 00          	rol    dx,0x0
  1b:	66 c1 c0 00          	rol    ax,0x0
  1f:	66 41 c1 c2 00       	rol    r10w,0x0
  24:	66 41 c1 c3 00       	rol    r11w,0x0
  29:	66 41 c1 c4 00       	rol    r12w,0x0
  2e:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.52
- Reference cycles: 3.68
- UOPS_PORT_6: 5.51
- UOPS_PORT_0: 5.49

⇨ One μop that can only use ports {'0', '6'}

With blocking instructions for ports {'2', '3'}:

Code:

   0:	45 8b 56 40          	mov    r10d,DWORD PTR [r14+0x40]
   4:	45 8b 5e 44          	mov    r11d,DWORD PTR [r14+0x44]
   8:	45 8b 66 48          	mov    r12d,DWORD PTR [r14+0x48]
   c:	41 8b 5e 4c          	mov    ebx,DWORD PTR [r14+0x4c]
  10:	41 8b 4e 50          	mov    ecx,DWORD PTR [r14+0x50]
  14:	41 8b 56 54          	mov    edx,DWORD PTR [r14+0x54]
  18:	41 8b 46 58          	mov    eax,DWORD PTR [r14+0x58]
  1c:	45 8b 56 40          	mov    r10d,DWORD PTR [r14+0x40]
  20:	45 8b 5e 44          	mov    r11d,DWORD PTR [r14+0x44]
  24:	45 8b 66 48          	mov    r12d,DWORD PTR [r14+0x48]
  28:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.6
- Reference cycles: 3.99
- UOPS_PORT_2: 5.5
- UOPS_PORT_3: 5.5

⇨ One μop that can only use ports {'2', '3'}

With an indexed addressing mode

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c2 00       	rol    r10w,0x0
   5:	66 41 c1 c3 00       	rol    r11w,0x0
   a:	66 41 c1 c4 00       	rol    r12w,0x0
   f:	66 c1 c3 00          	rol    bx,0x0
  13:	66 c1 c1 00          	rol    cx,0x0
  17:	66 c1 c2 00          	rol    dx,0x0
  1b:	66 c1 c0 00          	rol    ax,0x0
  1f:	66 41 c1 c2 00       	rol    r10w,0x0
  24:	66 41 c1 c3 00       	rol    r11w,0x0
  29:	66 41 c1 c4 00       	rol    r12w,0x0
  2e:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.55
- Reference cycles: 3.99
- UOPS_PORT_6: 5.51
- UOPS_PORT_0: 5.49

⇨ One μop that can only use ports {'0', '6'}

With blocking instructions for ports {'2', '3'}:

Code:

   0:	45 8b 56 40          	mov    r10d,DWORD PTR [r14+0x40]
   4:	45 8b 5e 44          	mov    r11d,DWORD PTR [r14+0x44]
   8:	45 8b 66 48          	mov    r12d,DWORD PTR [r14+0x48]
   c:	41 8b 5e 4c          	mov    ebx,DWORD PTR [r14+0x4c]
  10:	41 8b 4e 50          	mov    ecx,DWORD PTR [r14+0x50]
  14:	41 8b 56 54          	mov    edx,DWORD PTR [r14+0x54]
  18:	41 8b 46 58          	mov    eax,DWORD PTR [r14+0x58]
  1c:	45 8b 56 40          	mov    r10d,DWORD PTR [r14+0x40]
  20:	45 8b 5e 44          	mov    r11d,DWORD PTR [r14+0x44]
  24:	45 8b 66 48          	mov    r12d,DWORD PTR [r14+0x48]
  28:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.59
- Reference cycles: 3.68
- UOPS_PORT_2: 5.5
- UOPS_PORT_3: 5.5

⇨ One μop that can only use ports {'2', '3'}