SHLX (R64, M64, R64) - Throughput and Uops (IACA 2.1)
With a non-indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 0.50 Cycles Throughput Bottleneck: Port0, PORT2_AGU, Port2_DATA, PORT3_AGU, Port3_DATA, Port6
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.5 0.0 | 0.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 | 0.5 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2^ | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx r8, qword ptr [r14], r9
Total Num Of Uops: 2
With 7 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 3.50 Cycles Throughput Bottleneck: Port0, PORT2_AGU, Port2_DATA, PORT3_AGU, Port3_DATA, Port6
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 3.5 0.0 | 0.0 | 3.5 3.5 | 3.5 3.5 | 0.0 | 0.0 | 3.5 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2^ | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx r8, qword ptr [r14], r9
| 2^ | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx r10, qword ptr [r14+0x8], r9
| 2^ | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx r11, qword ptr [r14+0x10], r9
| 2^ | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx r12, qword ptr [r14+0x18], r9
| 2^ | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx rbx, qword ptr [r14+0x20], r9
| 2^ | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx rcx, qword ptr [r14+0x28], r9
| 2^ | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx rdx, qword ptr [r14+0x30], r9
Total Num Of Uops: 14
With an indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 0.50 Cycles Throughput Bottleneck: FrontEnd, Port0, PORT2_AGU, Port2_DATA, PORT3_AGU, Port3_DATA, Port6
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.5 0.0 | 0.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 | 0.5 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2 | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx r8, qword ptr [r14+r13*1], r9
Total Num Of Uops: 2
With 7 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 3.50 Cycles Throughput Bottleneck: FrontEnd, Port0, PORT2_AGU, Port2_DATA, PORT3_AGU, Port3_DATA, Port6
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 3.5 0.0 | 0.0 | 3.5 3.5 | 3.5 3.5 | 0.0 | 0.0 | 3.5 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2 | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx r8, qword ptr [r14+r13*1], r9
| 2 | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx r10, qword ptr [r14+r13*1+0x8], r9
| 2 | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx r11, qword ptr [r14+r13*1+0x10], r9
| 2 | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx r12, qword ptr [r14+r13*1+0x18], r9
| 2 | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx rbx, qword ptr [r14+r13*1+0x20], r9
| 2 | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx rcx, qword ptr [r14+r13*1+0x28], r9
| 2 | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx rdx, qword ptr [r14+r13*1+0x30], r9
Total Num Of Uops: 14
With the -no_interiteration flag
Throughput Analysis Report
--------------------------
Block Throughput: 0.50 Cycles Throughput Bottleneck: Port0, PORT2_AGU, Port2_DATA, PORT3_AGU, Port3_DATA, Port6
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.5 0.0 | 0.0 | 0.5 0.5 | 0.5 0.5 | 0.0 | 0.0 | 0.5 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2^ | 0.5 | | 0.5 0.5 | 0.5 0.5 | | | 0.5 | | CP | shlx r8, qword ptr [r14], r9
Total Num Of Uops: 2