SHLX (R64, M64, R64) - Port Usage

With lfence (to avoid incorrect counts due to replays)

Code:

   0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop
   c:	90                   	nop
   d:	90                   	nop
   e:	90                   	nop
   f:	0f ae e8             	lfence

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 19.0
- Reference cycles: 13.13
- UOPS_DISPATCHED.INT_EU_ALL: 2.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.LD: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 0.0
- UOPS_DISPATCHED.SHIFT: 1.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 0.0

No uops

With an indexed addressing mode

With lfence (to avoid incorrect counts due to replays)

Code:

   0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
   6:	90                   	nop
   7:	90                   	nop
   8:	90                   	nop
   9:	90                   	nop
   a:	90                   	nop
   b:	90                   	nop
   c:	90                   	nop
   d:	90                   	nop
   e:	90                   	nop
   f:	90                   	nop
  10:	0f ae e8             	lfence

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 19.0
- Reference cycles: 13.47
- UOPS_DISPATCHED.INT_EU_ALL: 2.0
- UOPS_DISPATCHED.ALU: 1.0
- UOPS_DISPATCHED.LD: 1.0
- UOPS_DISPATCHED.SLOW: 0.0
- UOPS_DISPATCHED.STD: 0.0
- UOPS_DISPATCHED.SHIFT: 1.0
- UOPS_DISPATCHED.JMP: 0.0
- UOPS_DISPATCHED.STA: 0.0

No uops