SHLX (R64, M64, R64) - Throughput and Uops

With unroll_count=500 and no inner loop

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.0
  • Reference cycles: 0.64
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 0.98
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 0.98
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.01
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 0.99
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	90                   	nop
     6:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 1.01
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.02

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	90                   	nop
     6:	90                   	nop
     7:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 1.0
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 5.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.01

With unroll_count=500, no inner loop, and 4 NOPs

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	90                   	nop
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 1.01
  • Reference cycles: 0.74
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 6.0
  • UOPS_MITE: 6.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.02

With unroll_count=500, no inner loop, and 5 NOPs

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	90                   	nop
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 1.01
  • Reference cycles: 0.81
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 7.0
  • UOPS_MITE: 7.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.02

With unroll_count=500, no inner loop, and 6 NOPs

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	90                   	nop
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 7.0
  • Core cycles: 1.03
  • Reference cycles: 0.77
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.03

With unroll_count=500, no inner loop, and 7 NOPs

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	90                   	nop
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
     b:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 2.0
  • Reference cycles: 1.38
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 9.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.01

With loop_count=1000 and unroll_count=10

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 0.51
  • Reference cycles: 0.36
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.44
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.33
  • UOPS_DISPATCHED.JMP: 0.1
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 0.51
  • Reference cycles: 0.36
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.35
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.34
  • UOPS_DISPATCHED.JMP: 0.01
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	c4 42 b1 f7 56 08    	shlx   r10,QWORD PTR [r14+0x8],r9
     b:	c4 42 b1 f7 5e 10    	shlx   r11,QWORD PTR [r14+0x10],r9
    11:	c4 42 b1 f7 66 18    	shlx   r12,QWORD PTR [r14+0x18],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 2.78
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 4.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 4.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	c4 42 b1 f7 56 08    	shlx   r10,QWORD PTR [r14+0x8],r9
     b:	c4 42 b1 f7 5e 10    	shlx   r11,QWORD PTR [r14+0x10],r9
    11:	c4 42 b1 f7 66 18    	shlx   r12,QWORD PTR [r14+0x18],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 1.37
  • Reference cycles: 0.98
  • UOPS_EXECUTED.THREAD: 8.51
  • RETIRE_SLOTS: 8.51
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 4.53
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 4.03
  • UOPS_DISPATCHED.JMP: 0.5
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	c4 42 b1 f7 56 08    	shlx   r10,QWORD PTR [r14+0x8],r9
     b:	c4 42 b1 f7 5e 10    	shlx   r11,QWORD PTR [r14+0x10],r9
    11:	c4 42 b1 f7 66 18    	shlx   r12,QWORD PTR [r14+0x18],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 1.38
  • Reference cycles: 0.96
  • UOPS_EXECUTED.THREAD: 8.06
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 0.07
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 4.07
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 4.01
  • UOPS_DISPATCHED.JMP: 0.05
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With unroll_count=100 and no inner loop

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	c4 42 b1 f7 56 08    	shlx   r10,QWORD PTR [r14+0x8],r9
     b:	c4 42 b1 f7 5e 10    	shlx   r11,QWORD PTR [r14+0x10],r9
    11:	c4 42 b1 f7 66 18    	shlx   r12,QWORD PTR [r14+0x18],r9
    17:	c4 c2 b1 f7 5e 20    	shlx   rbx,QWORD PTR [r14+0x20],r9
    1d:	c4 c2 b1 f7 4e 28    	shlx   rcx,QWORD PTR [r14+0x28],r9
    23:	c4 c2 b1 f7 56 30    	shlx   rdx,QWORD PTR [r14+0x30],r9
    29:	c4 c2 b1 f7 46 38    	shlx   rax,QWORD PTR [r14+0x38],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 7.99
  • Reference cycles: 5.39
  • UOPS_EXECUTED.THREAD: 16.0
  • RETIRE_SLOTS: 16.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 8.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 8.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.01

With loop_count=1000 and unroll_count=1

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	c4 42 b1 f7 56 08    	shlx   r10,QWORD PTR [r14+0x8],r9
     b:	c4 42 b1 f7 5e 10    	shlx   r11,QWORD PTR [r14+0x10],r9
    11:	c4 42 b1 f7 66 18    	shlx   r12,QWORD PTR [r14+0x18],r9
    17:	c4 c2 b1 f7 5e 20    	shlx   rbx,QWORD PTR [r14+0x20],r9
    1d:	c4 c2 b1 f7 4e 28    	shlx   rcx,QWORD PTR [r14+0x28],r9
    23:	c4 c2 b1 f7 56 30    	shlx   rdx,QWORD PTR [r14+0x30],r9
    29:	c4 c2 b1 f7 46 38    	shlx   rax,QWORD PTR [r14+0x38],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 2.72
  • Reference cycles: 1.92
  • UOPS_EXECUTED.THREAD: 17.02
  • RETIRE_SLOTS: 17.01
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 9.05
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 8.05
  • UOPS_DISPATCHED.JMP: 1.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c4 42 b1 f7 06       	shlx   r8,QWORD PTR [r14],r9
     5:	c4 42 b1 f7 56 08    	shlx   r10,QWORD PTR [r14+0x8],r9
     b:	c4 42 b1 f7 5e 10    	shlx   r11,QWORD PTR [r14+0x10],r9
    11:	c4 42 b1 f7 66 18    	shlx   r12,QWORD PTR [r14+0x18],r9
    17:	c4 c2 b1 f7 5e 20    	shlx   rbx,QWORD PTR [r14+0x20],r9
    1d:	c4 c2 b1 f7 4e 28    	shlx   rcx,QWORD PTR [r14+0x28],r9
    23:	c4 c2 b1 f7 56 30    	shlx   rdx,QWORD PTR [r14+0x30],r9
    29:	c4 c2 b1 f7 46 38    	shlx   rax,QWORD PTR [r14+0x38],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 2.71
  • Reference cycles: 1.94
  • UOPS_EXECUTED.THREAD: 16.11
  • RETIRE_SLOTS: 16.11
  • UOPS_MITE: 0.15
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 8.12
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 8.03
  • UOPS_DISPATCHED.JMP: 0.1
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.08

With unroll_count=500 and no inner loop

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.0
  • Core cycles: 1.0
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 2.0
  • UOPS_MITE: 2.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 0.99
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 0.98
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 2.0
  • Core cycles: 1.01
  • Reference cycles: 0.64
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 3.0
  • UOPS_MITE: 3.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.02

With unroll_count=500, no inner loop, and 2 NOPs

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	90                   	nop
     7:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 3.0
  • Core cycles: 1.0
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 4.0
  • UOPS_MITE: 4.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.01

With unroll_count=500, no inner loop, and 3 NOPs

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 1.02
  • Reference cycles: 0.67
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 5.0
  • UOPS_MITE: 5.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.02

With unroll_count=500, no inner loop, and 4 NOPs

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 1.01
  • Reference cycles: 0.74
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 6.0
  • UOPS_MITE: 6.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.02

With unroll_count=500, no inner loop, and 5 NOPs

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 1.03
  • Reference cycles: 0.77
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 7.0
  • UOPS_MITE: 7.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.03

With unroll_count=500, no inner loop, and 6 NOPs

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
     b:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 7.0
  • Core cycles: 1.13
  • Reference cycles: 0.74
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 1.13

With unroll_count=500, no inner loop, and 7 NOPs

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	90                   	nop
     7:	90                   	nop
     8:	90                   	nop
     9:	90                   	nop
     a:	90                   	nop
     b:	90                   	nop
     c:	90                   	nop
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 2.0
  • Reference cycles: 1.55
  • UOPS_EXECUTED.THREAD: 2.0
  • RETIRE_SLOTS: 9.0
  • UOPS_MITE: 9.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.2
  • Core cycles: 0.51
  • Reference cycles: 0.36
  • UOPS_EXECUTED.THREAD: 2.1
  • RETIRE_SLOTS: 2.1
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.44
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.33
  • UOPS_DISPATCHED.JMP: 0.1
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 1.02
  • Core cycles: 0.51
  • Reference cycles: 0.36
  • UOPS_EXECUTED.THREAD: 2.01
  • RETIRE_SLOTS: 2.01
  • UOPS_MITE: 0.02
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 1.35
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 1.34
  • UOPS_DISPATCHED.JMP: 0.01
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With unroll_count=200 and no inner loop

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	c4 02 b1 f7 54 2e 08 	shlx   r10,QWORD PTR [r14+r13*1+0x8],r9
     d:	c4 02 b1 f7 5c 2e 10 	shlx   r11,QWORD PTR [r14+r13*1+0x10],r9
    14:	c4 02 b1 f7 64 2e 18 	shlx   r12,QWORD PTR [r14+r13*1+0x18],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.0
  • Core cycles: 4.0
  • Reference cycles: 3.03
  • UOPS_EXECUTED.THREAD: 8.0
  • RETIRE_SLOTS: 8.0
  • UOPS_MITE: 8.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 4.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 4.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 4.01

With loop_count=1000 and unroll_count=2

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	c4 02 b1 f7 54 2e 08 	shlx   r10,QWORD PTR [r14+r13*1+0x8],r9
     d:	c4 02 b1 f7 5c 2e 10 	shlx   r11,QWORD PTR [r14+r13*1+0x10],r9
    14:	c4 02 b1 f7 64 2e 18 	shlx   r12,QWORD PTR [r14+r13*1+0x18],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 5.0
  • Core cycles: 1.36
  • Reference cycles: 0.96
  • UOPS_EXECUTED.THREAD: 8.51
  • RETIRE_SLOTS: 8.51
  • UOPS_MITE: 0.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 4.53
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 4.03
  • UOPS_DISPATCHED.JMP: 0.5
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	c4 02 b1 f7 54 2e 08 	shlx   r10,QWORD PTR [r14+r13*1+0x8],r9
     d:	c4 02 b1 f7 5c 2e 10 	shlx   r11,QWORD PTR [r14+r13*1+0x10],r9
    14:	c4 02 b1 f7 64 2e 18 	shlx   r12,QWORD PTR [r14+r13*1+0x18],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 4.1
  • Core cycles: 1.36
  • Reference cycles: 0.94
  • UOPS_EXECUTED.THREAD: 8.06
  • RETIRE_SLOTS: 8.05
  • UOPS_MITE: 0.07
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 4.07
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 4.01
  • UOPS_DISPATCHED.JMP: 0.05
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.04

With unroll_count=100 and no inner loop

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	c4 02 b1 f7 54 2e 08 	shlx   r10,QWORD PTR [r14+r13*1+0x8],r9
     d:	c4 02 b1 f7 5c 2e 10 	shlx   r11,QWORD PTR [r14+r13*1+0x10],r9
    14:	c4 02 b1 f7 64 2e 18 	shlx   r12,QWORD PTR [r14+r13*1+0x18],r9
    1b:	c4 82 b1 f7 5c 2e 20 	shlx   rbx,QWORD PTR [r14+r13*1+0x20],r9
    22:	c4 82 b1 f7 4c 2e 28 	shlx   rcx,QWORD PTR [r14+r13*1+0x28],r9
    29:	c4 82 b1 f7 54 2e 30 	shlx   rdx,QWORD PTR [r14+r13*1+0x30],r9
    30:	c4 82 b1 f7 44 2e 38 	shlx   rax,QWORD PTR [r14+r13*1+0x38],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.0
  • Core cycles: 7.99
  • Reference cycles: 5.39
  • UOPS_EXECUTED.THREAD: 16.0
  • RETIRE_SLOTS: 16.0
  • UOPS_MITE: 16.0
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 8.0
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 8.0
  • UOPS_DISPATCHED.JMP: 0.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 8.01

With loop_count=1000 and unroll_count=1

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	c4 02 b1 f7 54 2e 08 	shlx   r10,QWORD PTR [r14+r13*1+0x8],r9
     d:	c4 02 b1 f7 5c 2e 10 	shlx   r11,QWORD PTR [r14+r13*1+0x10],r9
    14:	c4 02 b1 f7 64 2e 18 	shlx   r12,QWORD PTR [r14+r13*1+0x18],r9
    1b:	c4 82 b1 f7 5c 2e 20 	shlx   rbx,QWORD PTR [r14+r13*1+0x20],r9
    22:	c4 82 b1 f7 4c 2e 28 	shlx   rcx,QWORD PTR [r14+r13*1+0x28],r9
    29:	c4 82 b1 f7 54 2e 30 	shlx   rdx,QWORD PTR [r14+r13*1+0x30],r9
    30:	c4 82 b1 f7 44 2e 38 	shlx   rax,QWORD PTR [r14+r13*1+0x38],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 10.0
  • Core cycles: 2.73
  • Reference cycles: 1.95
  • UOPS_EXECUTED.THREAD: 17.02
  • RETIRE_SLOTS: 17.01
  • UOPS_MITE: 0.01
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 9.04
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 8.04
  • UOPS_DISPATCHED.JMP: 1.0
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

• Code:

     0:	c4 02 b1 f7 04 2e    	shlx   r8,QWORD PTR [r14+r13*1],r9
     6:	c4 02 b1 f7 54 2e 08 	shlx   r10,QWORD PTR [r14+r13*1+0x8],r9
     d:	c4 02 b1 f7 5c 2e 10 	shlx   r11,QWORD PTR [r14+r13*1+0x10],r9
    14:	c4 02 b1 f7 64 2e 18 	shlx   r12,QWORD PTR [r14+r13*1+0x18],r9
    1b:	c4 82 b1 f7 5c 2e 20 	shlx   rbx,QWORD PTR [r14+r13*1+0x20],r9
    22:	c4 82 b1 f7 4c 2e 28 	shlx   rcx,QWORD PTR [r14+r13*1+0x28],r9
    29:	c4 82 b1 f7 54 2e 30 	shlx   rdx,QWORD PTR [r14+r13*1+0x30],r9
    30:	c4 82 b1 f7 44 2e 38 	shlx   rax,QWORD PTR [r14+r13*1+0x38],r9
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  XOR R13, R13

• Show nanoBench command
• Results:
  • Instructions retired: 8.2
  • Core cycles: 2.7
  • Reference cycles: 1.9
  • UOPS_EXECUTED.THREAD: 16.12
  • RETIRE_SLOTS: 16.11
  • UOPS_MITE: 0.14
  • UOPS_MS: 0.0
  • UOPS_DISPATCHED.INT_EU_ALL: 8.13
  • UOPS_DISPATCHED.ALU: 0.0
  • UOPS_DISPATCHED.SLOW: 0.0
  • UOPS_DISPATCHED.STD: 0.0
  • UOPS_DISPATCHED.SHIFT: 8.03
  • UOPS_DISPATCHED.JMP: 0.1
  • UOPS_DISPATCHED.STA: 0.0
  • UOPS_DISPATCHED.V0: 0.0
  • UOPS_DISPATCHED.V1: 0.0
  • UOPS_DISPATCHED.V2: 0.0
  • UOPS_DISPATCHED.V3: 0.0
  • DIV_CYCLES: 0.0
  • ILD_STALL.LCP: 0.0
  • UOPS_MITE>=1: 0.08