VGATHERQPD (YMM, VSIB_YMM, YMM)

Operands

• Operand 1 (r/w): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)
• Operand 2 (r): Memory
• Operand 3 (r/w): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)

Available performance data

• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤25
  • Latency operand 2 → 1 (address, index register): ≤29
  • Latency operand 2 → 1 (memory): ≤22
  • Latency operand 2 → 3 (address, base register): ≤0
  • Latency operand 2 → 3 (address, index register): ≤1
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 29
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 1.33
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 7
  • Retire slots: 5
  • Decoded (MITE): 5
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p015+2*p15+4*p23A

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 1: 21
  • Latency operand 1 → 3: 13
  • Latency operand 2 → 1 (address, base register): ≤19
  • Latency operand 2 → 1 (address, index register): ≤24
  • Latency operand 2 → 1 (memory): ≤15
  • Latency operand 2 → 3 (address, base register): ≤6
  • Latency operand 2 → 3 (address, index register): ≤14
  • Latency operand 2 → 3 (memory): ≤5
  • Latency operand 3 → 1: 22
  • Latency operand 3 → 3: 13
• Throughput
  • Measured (loop): 22.17
  • Measured (unrolled): 23.80
• Number of μops
  • Executed: 40
  • Microcode Sequencer (MS): 39
  • Requires the complex decoder

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤16
  • Latency operand 2 → 1 (address, index register): ≤20
  • Latency operand 2 → 1 (memory): ≤13
  • Latency operand 2 → 3 (address, base register): ≤0
  • Latency operand 2 → 3 (address, index register): ≤0
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 20
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 3.00
  • Measured (unrolled): 3.00
• Number of μops
  • Executed: 5
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p015+1*p15+4*p23

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤16
  • Latency operand 2 → 1 (address, index register): ≤20
  • Latency operand 2 → 1 (memory): ≤13
  • Latency operand 2 → 3 (address, base register): ≤0
  • Latency operand 2 → 3 (address, index register): ≤0
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 20
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 3.00
  • Measured (unrolled): 3.00
• Number of μops
  • Executed: 5
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p015+1*p15+4*p23

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤16
  • Latency operand 2 → 1 (address, index register): ≤20
  • Latency operand 2 → 1 (memory): ≤13
  • Latency operand 2 → 3 (address, base register): ≤0
  • Latency operand 2 → 3 (address, index register): ≤0
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 20
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 3.00
  • Measured (unrolled): 3.00
• Number of μops
  • Executed: 5
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p015+1*p15+4*p23

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤16
  • Latency operand 2 → 1 (address, index register): ≤20
  • Latency operand 2 → 1 (memory): ≤13
  • Latency operand 2 → 3 (address, base register): ≤0
  • Latency operand 2 → 3 (address, index register): ≤0
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 20
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 4.00
  • Measured (unrolled): 4.00
• Number of μops
  • Executed: 5
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p015+4*p23+1*p5

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤16
  • Latency operand 2 → 1 (address, index register): ≤20
  • Latency operand 2 → 1 (memory): ≤13
  • Latency operand 2 → 3 (address, base register): ≤0
  • Latency operand 2 → 3 (address, index register): ≤0
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 20
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 3.00
  • Measured (unrolled): 3.00
• Number of μops
  • Executed: 5
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p015+4*p23+1*p5

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤16
  • Latency operand 2 → 1 (address, index register): ≤20
  • Latency operand 2 → 1 (memory): ≤13
  • Latency operand 2 → 3 (address, base register): ≤0
  • Latency operand 2 → 3 (address, index register): ≤0
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 20
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 4.00
  • Measured (unrolled): 4.00
• Number of μops
  • Executed: 5
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p015+4*p23+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 3.21
• Number of μops: 5
• Port usage: 1*p0+1*p015+4*p23+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.99
• Number of μops: 5
• Port usage: 1*p0+1*p015+4*p23+1*p5

Coffee Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤16
  • Latency operand 2 → 1 (address, index register): ≤20
  • Latency operand 2 → 1 (memory): ≤13
  • Latency operand 2 → 3 (address, base register): ≤0
  • Latency operand 2 → 3 (address, index register): ≤0
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 20
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 4.00
  • Measured (unrolled): 4.00
• Number of μops
  • Executed: 5
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p015+4*p23+1*p5

Kaby Lake

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤16
  • Latency operand 2 → 1 (address, index register): ≤20
  • Latency operand 2 → 1 (memory): ≤13
  • Latency operand 2 → 3 (address, base register): ≤0
  • Latency operand 2 → 3 (address, index register): ≤0
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 20
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 4.00
  • Measured (unrolled): 4.00
• Number of μops
  • Executed: 5
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p015+4*p23+1*p5

Skylake

• Measurements
• Latencies
  • Latency operand 1 → 1: 1
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤16
  • Latency operand 2 → 1 (address, index register): ≤20
  • Latency operand 2 → 1 (memory): ≤13
  • Latency operand 2 → 3 (address, base register): ≤0
  • Latency operand 2 → 3 (address, index register): ≤1
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 20
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 4.00
  • Measured (unrolled): 4.00
• Number of μops
  • Executed: 5
  • Retire slots: 4
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p015+4*p23+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 3.21
• Number of μops: 5
• Port usage: 1*p0+1*p015+4*p23+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.99
• Number of μops: 5
• Port usage: 1*p0+1*p015+4*p23+1*p5

Broadwell

• Measurements
• Latencies
  • Latency operand 1 → 1: 2
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤12
  • Latency operand 2 → 1 (address, index register): ≤18
  • Latency operand 2 → 1 (memory): ≤11
  • Latency operand 2 → 3 (address, base register): ≤0
  • Latency operand 2 → 3 (address, index register): ≤3
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 18
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 3.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 8
  • Retire slots: 9
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 5
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 4*p23+1*p4+3*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 3.00
  • IACA: 6.00 (with the -no_interiteration flag: 7.29)
• Number of μops: 8
• Port usage: 1*p0156+4*p23+3*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 3.00
  • IACA: 6.00
• Number of μops: 8
• Port usage: 1*p0156+4*p23+3*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 3.00
  • IACA: 5.99
• Number of μops: 9
• Port usage: 1*p0156+4*p23+1*p4+3*p5

Haswell

• Measurements
• Latencies
  • Latency operand 1 → 1: 2
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤12
  • Latency operand 2 → 1 (address, index register): ≤17
  • Latency operand 2 → 1 (memory): ≤11
  • Latency operand 2 → 3 (address, base register): ≤0
  • Latency operand 2 → 3 (address, index register): ≤4
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 18
  • Latency operand 3 → 3: 3
• Throughput
  • Computed from the port usage: 5.00
  • Measured (loop): 8.00
  • Measured (unrolled): 8.00
• Number of μops
  • Executed: 22
  • Retire slots: 22
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 19
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 5*p0+3*p015+5*p06+1*p15+4*p23+4*p5
• IACA 2.1
• Latency: 14
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 8.50 (with the -no_interiteration flag: 8.50)
• Number of μops: 5
• Port usage: 1*p0+1*p0156+4*p23+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 5.00
  • IACA: 7.00 (with the -no_interiteration flag: 7.95)
• Number of μops: 22
• Port usage: 5*p0+5*p015+4*p06+1*p15+4*p23+3*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 5.00
  • IACA: 7.00
• Number of μops: 22
• Port usage: 5*p0+5*p015+4*p06+1*p15+4*p23+3*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 5.00
  • IACA: 7.30
• Number of μops: 22
• Port usage: 5*p0+5*p015+4*p06+1*p15+4*p23+3*p5

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1: 4
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤16
  • Latency operand 2 → 1 (address, index register): ≤16
  • Latency operand 2 → 1 (memory): ≤12
  • Latency operand 2 → 3 (address, base register): ≤1
  • Latency operand 2 → 3 (address, index register): ≤0
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 15
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 2.50
  • Measured (loop): 4.00
  • Measured (unrolled): 4.00
• Number of μops
  • Executed: 24
• Port usage: 4*FP01+1*FP0123+2*FP123+1*FP23+5*FP45

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 1 → 1: 4
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤16
  • Latency operand 2 → 1 (address, index register): ≤18
  • Latency operand 2 → 1 (memory): ≤12
  • Latency operand 2 → 3 (address, base register): ≤2
  • Latency operand 2 → 3 (address, index register): ≤0
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 15
  • Latency operand 3 → 3: 0
• Throughput
  • Computed from the port usage: 2.50
  • Measured (loop): 4.00
  • Measured (unrolled): 4.00
• Number of μops
  • Executed: 23
• Port usage: 2*FP01+2*FP0123+2*FP1+1*FP12+5*FP45
• Documentation
• Number of μops: ucode

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 1 → 1: 4
  • Latency operand 1 → 3: 0
  • Latency operand 2 → 1 (address, base register): ≤18
  • Latency operand 2 → 1 (address, index register): ≤18
  • Latency operand 2 → 1 (memory): ≤11
  • Latency operand 2 → 3 (address, base register): ≤2
  • Latency operand 2 → 3 (address, index register): ≤2
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 18
  • Latency operand 3 → 3: 0
• Throughput
  • Measured (loop): 9.00
  • Measured (unrolled): 9.00
• Number of μops
  • Executed: 32
• Documentation
• Number of μops: ucode

AMD Zen+

• Measurements
• Latencies
  • Latency operand 1 → 1: 5
  • Latency operand 1 → 3: 3
  • Latency operand 2 → 1 (address, base register): ≤15
  • Latency operand 2 → 1 (address, index register): ≤16
  • Latency operand 2 → 1 (memory): ≤9
  • Latency operand 2 → 3 (address, base register): ≤3
  • Latency operand 2 → 3 (address, index register): ≤4
  • Latency operand 2 → 3 (memory): ≤0
  • Latency operand 3 → 1: 16
  • Latency operand 3 → 3: 3
• Throughput
  • Measured (loop): 12.00
  • Measured (unrolled): 12.00
• Number of μops
  • Executed: 34
• Documentation
• Latency: 16
• Throughput: 12.00
• Number of μops: ucode