VGATHERQPD (YMM, VSIB

Experiment 1

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instruction: VPCMPEQD YMM1, YMM1, YMM1

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.0
- Reference cycles: 3.54
- UOPS_EXECUTED.THREAD: 5.99

Experiment 2

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 7

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 8.0
- Reference cycles: 6.04
- UOPS_EXECUTED.THREAD: 13.01

Experiment 3

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 7

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 8.0
- Reference cycles: 6.25
- UOPS_EXECUTED.THREAD: 13.02

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instruction: VPCMPEQD YMM1, YMM1, YMM1

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM0, [R14+YMM14], YMM1;
VGATHERQPD YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.0
- Reference cycles: 3.75
- UOPS_EXECUTED.THREAD: 6.01

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 7

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM0, [R14+YMM14], YMM1;
VGATHERQPD YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 8.0
- Reference cycles: 6.25
- UOPS_EXECUTED.THREAD: 13.01

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 7

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM0, [R14+YMM14], YMM1;
VGATHERQPD YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 8.0
- Reference cycles: 6.04
- UOPS_EXECUTED.THREAD: 13.01

Latency operand 1 → 3: 0

Experiment 1

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 7

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 8.0
- Reference cycles: 6.25
- UOPS_EXECUTED.THREAD: 13.01

Experiment 2

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 7

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 6.0
- Reference cycles: 4.17
- UOPS_EXECUTED.THREAD: 13.01

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 7

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM0, [R14+YMM14], YMM1;
VGATHERQPD YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 8.0
- Reference cycles: 6.25
- UOPS_EXECUTED.THREAD: 13.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: 7

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM0, [R14+YMM14], YMM1;
VGATHERQPD YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 6.0
- Reference cycles: 4.58
- UOPS_EXECUTED.THREAD: 13.0

Latency operand 2 → 1 (address, base register): ≤16

Experiment 1

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥7

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 23.0
- Reference cycles: 16.67
- UOPS_EXECUTED.THREAD: 13.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥7

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM0, [R14+YMM14], YMM1;
VGATHERQPD YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 23.0
- Reference cycles: 17.29
- UOPS_EXECUTED.THREAD: 13.03

Latency operand 2 → 1 (address, index register): ≤20

Experiment 1

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥6

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   e:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  12:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  16:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1e:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 26.0
- Reference cycles: 19.17
- UOPS_EXECUTED.THREAD: 12.02

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥6

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   e:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  12:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  16:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1e:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM0, [R14+YMM14], YMM1;
VGATHERQPD YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 26.0
- Reference cycles: 18.96
- UOPS_EXECUTED.THREAD: 12.0

Latency operand 2 → 1 (memory): ≤13

Experiment 1

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVSD [R14], XMM13;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥8

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   b:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  11:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  17:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1d:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  23:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  29:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  2f:	c4 41 7b 11 2e       	vmovsd QWORD PTR [r14],xmm13
  34:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 21.0
- Reference cycles: 18.13
- UOPS_EXECUTED.THREAD: 14.99

Experiment 2

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVQ [R14], XMM13;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥8

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   a:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
   f:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  14:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  19:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1e:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  23:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  28:	c4 41 79 d6 2e       	vmovq  QWORD PTR [r14],xmm13
  2d:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 21.0
- Reference cycles: 18.75
- UOPS_EXECUTED.THREAD: 15.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVSD [R14], XMM13;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥8

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   b:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  11:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  17:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1d:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  23:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  29:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  2f:	c4 41 7b 11 2e       	vmovsd QWORD PTR [r14],xmm13
  34:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM0, [R14+YMM14], YMM1;
VGATHERQPD YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 21.0
- Reference cycles: 18.75
- UOPS_EXECUTED.THREAD: 15.02

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM0, [R14+YMM14], YMM1
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVQ [R14], XMM13;VPCMPEQD YMM1, YMM1, YMM1
Chain latency: ≥8

Code:

   0:	c4 82 f5 93 04 36    	vgatherqpd ymm0,QWORD PTR [r14+ymm14*1],ymm1
   6:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   a:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
   f:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  14:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  19:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1e:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  23:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  28:	c4 41 79 d6 2e       	vmovq  QWORD PTR [r14],xmm13
  2d:	c5 f5 76 c9          	vpcmpeqd ymm1,ymm1,ymm1

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM0, [R14+YMM14], YMM1;
VGATHERQPD YMM1, [R14+YMM14], YMM0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 21.0
- Reference cycles: 17.5
- UOPS_EXECUTED.THREAD: 15.01

Latency operand 2 → 3 (address, base register): ≤0

Experiment 1

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥7

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 6.43
- Reference cycles: 5.42
- UOPS_EXECUTED.THREAD: 13.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥7

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12
  1d:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM1, [R14+YMM14], YMM0;
VGATHERQPD YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 6.19
- Reference cycles: 5.63
- UOPS_EXECUTED.THREAD: 13.0

Latency operand 2 → 3 (address, index register): ≤0

Experiment 1

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥6

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   e:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  12:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  16:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1e:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 6.68
- Reference cycles: 5.83
- UOPS_EXECUTED.THREAD: 12.01

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥6

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   e:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  12:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  16:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1a:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1e:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM1, [R14+YMM14], YMM0;
VGATHERQPD YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 6.94
- Reference cycles: 6.25
- UOPS_EXECUTED.THREAD: 12.0

Latency operand 2 → 3 (memory): ≤0

Experiment 1

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVSD [R14], XMM13;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥8

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   b:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  11:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  17:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1d:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  23:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  29:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  2f:	c4 41 7b 11 2e       	vmovsd QWORD PTR [r14],xmm13
  34:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.0
- Reference cycles: 7.92
- UOPS_EXECUTED.THREAD: 14.99

Experiment 2

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVQ [R14], XMM13;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥8

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   a:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
   f:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  14:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  19:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1e:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  23:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  28:	c4 41 79 d6 2e       	vmovq  QWORD PTR [r14],xmm13
  2d:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 6.0
- Reference cycles: 5.0
- UOPS_EXECUTED.THREAD: 15.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVSD [R14], XMM13;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥8

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   b:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  11:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  17:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1d:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  23:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  29:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  2f:	c4 41 7b 11 2e       	vmovsd QWORD PTR [r14],xmm13
  34:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM1, [R14+YMM14], YMM0;
VGATHERQPD YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.0
- Reference cycles: 7.5
- UOPS_EXECUTED.THREAD: 15.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVQ [R14], XMM13;VPCMPEQD YMM0, YMM0, YMM0
Chain latency: ≥8

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   a:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
   f:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  14:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  19:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1e:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  23:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  28:	c4 41 79 d6 2e       	vmovq  QWORD PTR [r14],xmm13
  2d:	c5 fd 76 c0          	vpcmpeqd ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM1, [R14+YMM14], YMM0;
VGATHERQPD YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 6.0
- Reference cycles: 3.96
- UOPS_EXECUTED.THREAD: 15.02

Latency operand 3 → 1: 20

Experiment 1

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM13, YMM13, YMM13;VORPD YMM0, YMM0, YMM13
Chain latency: 8

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  2e:	c4 c1 7d 56 c5       	vorpd  ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 28.0
- Reference cycles: 22.08
- UOPS_EXECUTED.THREAD: 14.0

Experiment 2

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM13, YMM13, YMM13;VPOR YMM0, YMM0, YMM13
Chain latency: 8

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  27:	c4 c1 7d eb c5       	vpor   ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 28.08
- Reference cycles: 22.5
- UOPS_EXECUTED.THREAD: 13.99

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM13, YMM13, YMM13;VORPD YMM0, YMM0, YMM13
Chain latency: 8

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  2e:	c4 c1 7d 56 c5       	vorpd  ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM1, [R14+YMM14], YMM0;
VGATHERQPD YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 28.0
- Reference cycles: 21.04
- UOPS_EXECUTED.THREAD: 14.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM13, YMM13, YMM13;VPOR YMM0, YMM0, YMM13
Chain latency: 8

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  27:	c4 c1 7d eb c5       	vpor   ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM1, [R14+YMM14], YMM0;
VGATHERQPD YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 27.99
- Reference cycles: 21.04
- UOPS_EXECUTED.THREAD: 14.03

Latency operand 3 → 3: 0

Experiment 1

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VPCMPEQD YMM13, YMM13, YMM13;VPOR YMM0, YMM0, YMM13
Chain latency: 1

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
   b:	c4 c1 7d eb c5       	vpor   ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 3.13
- UOPS_EXECUTED.THREAD: 7.01

Experiment 2

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM13, YMM13, YMM13;VORPD YMM0, YMM0, YMM13
Chain latency: 8

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  2e:	c4 c1 7d 56 c5       	vorpd  ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.0
- Reference cycles: 7.5
- UOPS_EXECUTED.THREAD: 13.99

Experiment 3

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM13, YMM13, YMM13;VPOR YMM0, YMM0, YMM13
Chain latency: 8

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  27:	c4 c1 7d eb c5       	vpor   ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 6.0
- Reference cycles: 5.21
- UOPS_EXECUTED.THREAD: 14.01

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VPCMPEQD YMM13, YMM13, YMM13;VPOR YMM0, YMM0, YMM13
Chain latency: 1

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
   b:	c4 c1 7d eb c5       	vpor   ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM1, [R14+YMM14], YMM0;
VGATHERQPD YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.0
- Reference cycles: 3.75
- UOPS_EXECUTED.THREAD: 7.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VPCMPEQD YMM13, YMM13, YMM13;VORPD YMM0, YMM0, YMM13
Chain latency: 8

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  29:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  2e:	c4 c1 7d 56 c5       	vorpd  ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM1, [R14+YMM14], YMM0;
VGATHERQPD YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.0
- Reference cycles: 7.5
- UOPS_EXECUTED.THREAD: 14.01

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERQPD YMM1, [R14+YMM14], YMM0
Chain instructions: VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPCMPEQD YMM13, YMM13, YMM13;VPOR YMM0, YMM0, YMM13
Chain latency: 8

Code:

   0:	c4 82 fd 93 0c 36    	vgatherqpd ymm1,QWORD PTR [r14+ymm14*1],ymm0
   6:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  1e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  22:	c4 41 15 76 ed       	vpcmpeqd ymm13,ymm13,ymm13
  27:	c4 c1 7d eb c5       	vpor   ymm0,ymm0,ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM14, YMM14, YMM14;
VGATHERQPD YMM1, [R14+YMM14], YMM0;
VGATHERQPD YMM0, [R14+YMM14], YMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 6.0
- Reference cycles: 4.58
- UOPS_EXECUTED.THREAD: 14.01

VGATHERQPD (YMM, VSIB_YMM, YMM) - Latency

Operands

Latency operand 1 → 1: 1

Latency operand 1 → 3: 0

Latency operand 2 → 1 (address, base register): ≤16

Latency operand 2 → 1 (address, index register): ≤20

Latency operand 2 → 1 (memory): ≤13

Latency operand 2 → 3 (address, base register): ≤0

Latency operand 2 → 3 (address, index register): ≤0

Latency operand 2 → 3 (memory): ≤0

Latency operand 3 → 1: 20

Latency operand 3 → 3: 0

Latency operand 1 → 1: 1

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 1 → 3: 0

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1 (address, base register): ≤16

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1 (address, index register): ≤20

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1 (memory): ≤13

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 3 (address, base register): ≤0

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 3 (address, index register): ≤0

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 3 (memory): ≤0

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 20

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 3: 0

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)