STMXCSR (M32)

Operands

• Operand 1 (w): Memory
• Operand 2 (r, suppressed): Register (MXCSR)

Available performance data

• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• Ivy Bridge
• Sandy Bridge
• Westmere
• Nehalem
• Wolfdale
• Conroe
• Tremont
• Goldmont Plus
• Goldmont
• Airmont
• Bonnell
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤0
  • Latency operand 1 → 1 (address, index register): ≤12
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p06+1*p49+1*p78

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
• Throughput
  • Measured (loop): 3.13
  • Measured (unrolled): 3.55
• Number of μops
  • Executed: 3
  • Microcode Sequencer (MS): 2
  • Requires the complex decoder

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤0
  • Latency operand 1 → 1 (address, index register): ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p06+1*p49+1*p78

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p06+1*p49+1*p78

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p06+1*p49+1*p78

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p06+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0+1*p06+1*p23+1*p4)

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p06+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0+1*p06+1*p23+1*p4)

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p06+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0+1*p06+1*p23+1*p4)
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 3
• Port usage: 1*p237+1*p4+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 0.85
• Number of μops: 3
• Port usage: 1*p237+1*p4+1*p5

Coffee Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p06+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0+1*p06+1*p23+1*p4)

Kaby Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p06+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0+1*p06+1*p23+1*p4)

Skylake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p06+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0+1*p06+1*p23+1*p4)
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 3
• Port usage: 1*p237+1*p4+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 0.85
• Number of μops: 3
• Port usage: 1*p237+1*p4+1*p5

Broadwell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤9
  • Latency operand 1 → 1 (address, index register): ≤9
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p06+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0+1*p06+1*p23+1*p4)
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p237+1*p4+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 3
• Port usage: 1*p237+1*p4+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 0.88
• Number of μops: 3
• Port usage: 1*p237+1*p4+1*p5

Haswell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤9
  • Latency operand 1 → 1 (address, index register): ≤9
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p06+1*p237+1*p4 (if an indexed addressing mode is used: 1*p0+1*p06+1*p23+1*p4)
• IACA 2.1
• Latency: 5
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p0+1*p06+1*p237+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p237+1*p4+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 3
• Port usage: 1*p237+1*p4+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 0.88
• Number of μops: 3
• Port usage: 1*p237+1*p4+1*p5

Ivy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤9
  • Latency operand 1 → 1 (address, index register): ≤9
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23+1*p4+1*p5
• IACA 2.1
• Latency: 5
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p0+1*p23+1*p4+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p0+1*p23+1*p4+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p0+1*p23+1*p4+1*p5

Sandy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤9
  • Latency operand 1 → 1 (address, index register): ≤9
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 4
  • Retire slots: 3 (if an indexed addressing mode is used: 4)
  • Decoded (MITE): 3
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23+1*p4+1*p5
• IACA 2.1
• Latency: 5
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p0+1*p23+1*p4+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p0+1*p23+1*p4+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 4
• Port usage: 1*p0+1*p23+1*p4+1*p5

Westmere

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤7
  • Latency operand 1 → 1 (address, index register): ≤7
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 2 (if an indexed addressing mode is used: 3)
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder
• Port usage: 1*p3+1*p4+1*p5
• IACA 2.1
• Latency: 4
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p3+1*p4+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p3+1*p4+1*p5

Nehalem

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤7
  • Latency operand 1 → 1 (address, index register): ≤7
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 2 (if an indexed addressing mode is used: 3)
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder
• Port usage: 1*p3+1*p4+1*p5
• IACA 2.1
• Latency: 4
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p3+1*p4+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p3+1*p4+1*p5

Wolfdale

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤23
  • Latency operand 1 → 1 (address, index register): ≤23
• Throughput
  • Computed from the port usage: 3.00
  • Measured (loop): 19.52
  • Measured (unrolled): 19.50
• Number of μops
  • Executed: 10
• Port usage: 5*p015+1*p3+1*p4+3*p5

Conroe

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤23
  • Latency operand 1 → 1 (address, index register): ≤23
• Throughput
  • Computed from the port usage: 2.67
  • Measured (loop): 19.52
  • Measured (unrolled): 19.50
• Number of μops
  • Executed: 10
• Port usage: 5*p015+1*p05+1*p3+1*p4+2*p5

Tremont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤3
  • Latency operand 1 → 1 (address, index register): ≤3
• Throughput
  • Measured (loop): 4.03
  • Measured (unrolled): 4.00
• Number of μops
  • Executed: 3
  • Microcode Sequencer (MS): 2
  • Requires the complex decoder

Goldmont Plus

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤14
  • Latency operand 1 → 1 (address, index register): ≤14
• Throughput
  • Measured (loop): 12.50
  • Measured (unrolled): 12.50
• Number of μops
  • Executed: 3
  • Microcode Sequencer (MS): 3
  • Requires the complex decoder

Goldmont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤13
  • Latency operand 1 → 1 (address, index register): ≤13
• Throughput
  • Measured (loop): 11.67
  • Measured (unrolled): 12.00
• Number of μops
  • Executed: 3
  • Microcode Sequencer (MS): 3
  • Requires the complex decoder

Airmont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
• Throughput
  • Measured (loop): 11.00
  • Measured (unrolled): 11.00
• Number of μops
  • Executed: 4
  • Microcode Sequencer (MS): 4
  • Requires the complex decoder

Bonnell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤15
  • Latency operand 1 → 1 (address, index register): ≤15
• Throughput
  • Measured (loop): 15.00
  • Measured (unrolled): 15.00
• Number of μops
  • Executed: 4
  • Microcode Sequencer (MS): 4
  • Requires the complex decoder

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤20
  • Latency operand 1 → 1 (address, index register): ≤20
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 15.10
  • Measured (unrolled): 15.09
• Number of μops
  • Executed: 2
• Port usage: 1*FP01+1*FP45

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤19
  • Latency operand 1 → 1 (address, index register): ≤19
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 15.10
  • Measured (unrolled): 15.10
• Number of μops
  • Executed: 2
• Port usage: 1*FP01+1*FP45
• Documentation
• Number of μops: ucode

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤19
  • Latency operand 1 → 1 (address, index register): ≤19
• Throughput
  • Measured (loop): 16.00
  • Measured (unrolled): 16.00
• Number of μops
  • Executed: 2
• Documentation
• Number of μops: ucode

AMD Zen+

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤18
  • Latency operand 1 → 1 (address, index register): ≤18
• Throughput
  • Measured (loop): 15.00
  • Measured (unrolled): 15.00
• Number of μops
  • Executed: 2
• Documentation
• Number of μops: ucode