STMXCSR (M32)

With unroll_count=500 and no inner loop

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.72
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.25
- UOPS_PORT_3: 0.38
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.37
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 0.72
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.37
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.13
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	90                   	nop
   5:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 2.0
- Reference cycles: 1.64
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.25
- UOPS_PORT_3: 0.34
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.41
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	90                   	nop
   5:	90                   	nop
   6:	90                   	nop

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.59
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.25
- UOPS_PORT_3: 0.25
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.1
- Reference cycles: 0.87
- UOPS_EXECUTED.THREAD: 4.11
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 3.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.31
- UOPS_PORT_3: 0.34
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.1
- UOPS_PORT_7: 0.36
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.1
- Reference cycles: 0.87
- UOPS_EXECUTED.THREAD: 4.11
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.31
- UOPS_PORT_3: 0.34
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.1
- UOPS_PORT_7: 0.36
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.01
- Reference cycles: 0.79
- UOPS_EXECUTED.THREAD: 4.02
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 3.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.27
- UOPS_PORT_3: 0.36
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.38
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.01
- Reference cycles: 0.8
- UOPS_EXECUTED.THREAD: 4.02
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.27
- UOPS_PORT_3: 0.36
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.38
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
   9:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
   e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.34
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.0
- UOPS_PORT_3: 1.5
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.0
- UOPS_PORT_7: 1.5
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
   9:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
   e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.51
- Reference cycles: 3.54
- UOPS_EXECUTED.THREAD: 16.53
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 12.56
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.22
- UOPS_PORT_3: 1.38
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.5
- UOPS_PORT_7: 1.41
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.02

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.51
- Reference cycles: 3.55
- UOPS_EXECUTED.THREAD: 16.53
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.22
- UOPS_PORT_3: 1.38
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.5
- UOPS_PORT_7: 1.41
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
   9:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
   e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.06
- Reference cycles: 3.2
- UOPS_EXECUTED.THREAD: 16.08
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 12.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.11
- UOPS_PORT_3: 1.39
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.05
- UOPS_PORT_7: 1.51
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.02

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.06
- Reference cycles: 3.2
- UOPS_EXECUTED.THREAD: 16.08
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 1.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 1.11
- UOPS_PORT_3: 1.39
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.05
- UOPS_PORT_7: 1.51
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.34

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
   9:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
   e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]
  13:	41 0f ae 5e 10       	stmxcsr DWORD PTR [r14+0x10]
  18:	41 0f ae 5e 14       	stmxcsr DWORD PTR [r14+0x14]
  1d:	41 0f ae 5e 18       	stmxcsr DWORD PTR [r14+0x18]
  22:	41 0f ae 5e 1c       	stmxcsr DWORD PTR [r14+0x1c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 6.42
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 24.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 3.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 8.0
- UOPS_PORT_7: 3.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
   9:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
   e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]
  13:	41 0f ae 5e 10       	stmxcsr DWORD PTR [r14+0x10]
  18:	41 0f ae 5e 14       	stmxcsr DWORD PTR [r14+0x14]
  1d:	41 0f ae 5e 18       	stmxcsr DWORD PTR [r14+0x18]
  22:	41 0f ae 5e 1c       	stmxcsr DWORD PTR [r14+0x1c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 9.03
- Reference cycles: 7.08
- UOPS_EXECUTED.THREAD: 33.06
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 25.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.44
- UOPS_PORT_3: 2.76
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 9.01
- UOPS_PORT_7: 2.83
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.04

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	41 0f ae 5e 10       	stmxcsr DWORD PTR [r14+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	41 0f ae 5e 14       	stmxcsr DWORD PTR [r14+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	41 0f ae 5e 18       	stmxcsr DWORD PTR [r14+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	41 0f ae 5e 1c       	stmxcsr DWORD PTR [r14+0x1c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 9.03
- Reference cycles: 7.08
- UOPS_EXECUTED.THREAD: 33.06
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.44
- UOPS_PORT_3: 2.76
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 9.01
- UOPS_PORT_7: 2.82
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
   9:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
   e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]
  13:	41 0f ae 5e 10       	stmxcsr DWORD PTR [r14+0x10]
  18:	41 0f ae 5e 14       	stmxcsr DWORD PTR [r14+0x14]
  1d:	41 0f ae 5e 18       	stmxcsr DWORD PTR [r14+0x18]
  22:	41 0f ae 5e 1c       	stmxcsr DWORD PTR [r14+0x1c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.13
- Reference cycles: 6.39
- UOPS_EXECUTED.THREAD: 32.16
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 24.21
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.22
- UOPS_PORT_3: 2.78
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 8.11
- UOPS_PORT_7: 3.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.04

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	41 0f ae 5e 10       	stmxcsr DWORD PTR [r14+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	41 0f ae 5e 14       	stmxcsr DWORD PTR [r14+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	41 0f ae 5e 18       	stmxcsr DWORD PTR [r14+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	41 0f ae 5e 1c       	stmxcsr DWORD PTR [r14+0x1c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.13
- Reference cycles: 6.47
- UOPS_EXECUTED.THREAD: 32.16
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.24
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.22
- UOPS_PORT_3: 2.78
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 8.11
- UOPS_PORT_7: 3.02
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
   9:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
   e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]
  13:	41 0f ae 5e 10       	stmxcsr DWORD PTR [r14+0x10]
  18:	41 0f ae 5e 14       	stmxcsr DWORD PTR [r14+0x14]
  1d:	41 0f ae 5e 18       	stmxcsr DWORD PTR [r14+0x18]
  22:	41 0f ae 5e 1c       	stmxcsr DWORD PTR [r14+0x1c]
  27:	41 0f ae 5e 20       	stmxcsr DWORD PTR [r14+0x20]
  2c:	41 0f ae 5e 24       	stmxcsr DWORD PTR [r14+0x24]
  31:	41 0f ae 5e 28       	stmxcsr DWORD PTR [r14+0x28]
  36:	41 0f ae 5e 2c       	stmxcsr DWORD PTR [r14+0x2c]
  3b:	41 0f ae 5e 30       	stmxcsr DWORD PTR [r14+0x30]
  40:	41 0f ae 5e 34       	stmxcsr DWORD PTR [r14+0x34]
  45:	41 0f ae 5e 38       	stmxcsr DWORD PTR [r14+0x38]
  4a:	41 0f ae 5e 3c       	stmxcsr DWORD PTR [r14+0x3c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 12.83
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 48.0
- UOPS_MITE: 48.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 6.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 16.0
- UOPS_PORT_7: 6.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
   9:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
   e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]
  13:	41 0f ae 5e 10       	stmxcsr DWORD PTR [r14+0x10]
  18:	41 0f ae 5e 14       	stmxcsr DWORD PTR [r14+0x14]
  1d:	41 0f ae 5e 18       	stmxcsr DWORD PTR [r14+0x18]
  22:	41 0f ae 5e 1c       	stmxcsr DWORD PTR [r14+0x1c]
  27:	41 0f ae 5e 20       	stmxcsr DWORD PTR [r14+0x20]
  2c:	41 0f ae 5e 24       	stmxcsr DWORD PTR [r14+0x24]
  31:	41 0f ae 5e 28       	stmxcsr DWORD PTR [r14+0x28]
  36:	41 0f ae 5e 2c       	stmxcsr DWORD PTR [r14+0x2c]
  3b:	41 0f ae 5e 30       	stmxcsr DWORD PTR [r14+0x30]
  40:	41 0f ae 5e 34       	stmxcsr DWORD PTR [r14+0x34]
  45:	41 0f ae 5e 38       	stmxcsr DWORD PTR [r14+0x38]
  4a:	41 0f ae 5e 3c       	stmxcsr DWORD PTR [r14+0x3c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 17.03
- Reference cycles: 13.4
- UOPS_EXECUTED.THREAD: 65.06
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 49.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.79
- UOPS_PORT_3: 5.32
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 17.01
- UOPS_PORT_7: 5.92
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.04

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	41 0f ae 5e 10       	stmxcsr DWORD PTR [r14+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	41 0f ae 5e 14       	stmxcsr DWORD PTR [r14+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	41 0f ae 5e 18       	stmxcsr DWORD PTR [r14+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	41 0f ae 5e 1c       	stmxcsr DWORD PTR [r14+0x1c]
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	40                   	rex
  4b:	41 0f ae 5e 20       	stmxcsr DWORD PTR [r14+0x20]
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	41 0f ae 5e 24       	stmxcsr DWORD PTR [r14+0x24]
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	40                   	rex
  5d:	41 0f ae 5e 28       	stmxcsr DWORD PTR [r14+0x28]
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	41 0f ae 5e 2c       	stmxcsr DWORD PTR [r14+0x2c]
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	40                   	rex
  6f:	41 0f ae 5e 30       	stmxcsr DWORD PTR [r14+0x30]
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	41 0f ae 5e 34       	stmxcsr DWORD PTR [r14+0x34]
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	40                   	rex
  81:	41 0f ae 5e 38       	stmxcsr DWORD PTR [r14+0x38]
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	41 0f ae 5e 3c       	stmxcsr DWORD PTR [r14+0x3c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 17.03
- Reference cycles: 13.4
- UOPS_EXECUTED.THREAD: 65.06
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 0.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.81
- UOPS_PORT_3: 5.31
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 17.01
- UOPS_PORT_7: 5.91
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
   9:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
   e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]
  13:	41 0f ae 5e 10       	stmxcsr DWORD PTR [r14+0x10]
  18:	41 0f ae 5e 14       	stmxcsr DWORD PTR [r14+0x14]
  1d:	41 0f ae 5e 18       	stmxcsr DWORD PTR [r14+0x18]
  22:	41 0f ae 5e 1c       	stmxcsr DWORD PTR [r14+0x1c]
  27:	41 0f ae 5e 20       	stmxcsr DWORD PTR [r14+0x20]
  2c:	41 0f ae 5e 24       	stmxcsr DWORD PTR [r14+0x24]
  31:	41 0f ae 5e 28       	stmxcsr DWORD PTR [r14+0x28]
  36:	41 0f ae 5e 2c       	stmxcsr DWORD PTR [r14+0x2c]
  3b:	41 0f ae 5e 30       	stmxcsr DWORD PTR [r14+0x30]
  40:	41 0f ae 5e 34       	stmxcsr DWORD PTR [r14+0x34]
  45:	41 0f ae 5e 38       	stmxcsr DWORD PTR [r14+0x38]
  4a:	41 0f ae 5e 3c       	stmxcsr DWORD PTR [r14+0x3c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.13
- Reference cycles: 12.68
- UOPS_EXECUTED.THREAD: 64.16
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 48.21
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.34
- UOPS_PORT_3: 5.67
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 16.11
- UOPS_PORT_7: 6.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.04

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	40                   	rex
   4:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	40                   	rex
   c:	41 0f ae 5e 04       	stmxcsr DWORD PTR [r14+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	40                   	rex
  15:	41 0f ae 5e 08       	stmxcsr DWORD PTR [r14+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	40                   	rex
  1e:	41 0f ae 5e 0c       	stmxcsr DWORD PTR [r14+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	40                   	rex
  27:	41 0f ae 5e 10       	stmxcsr DWORD PTR [r14+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	40                   	rex
  30:	41 0f ae 5e 14       	stmxcsr DWORD PTR [r14+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	40                   	rex
  39:	41 0f ae 5e 18       	stmxcsr DWORD PTR [r14+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	40                   	rex
  42:	41 0f ae 5e 1c       	stmxcsr DWORD PTR [r14+0x1c]
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	40                   	rex
  4b:	41 0f ae 5e 20       	stmxcsr DWORD PTR [r14+0x20]
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	40                   	rex
  54:	41 0f ae 5e 24       	stmxcsr DWORD PTR [r14+0x24]
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	40                   	rex
  5d:	41 0f ae 5e 28       	stmxcsr DWORD PTR [r14+0x28]
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	40                   	rex
  66:	41 0f ae 5e 2c       	stmxcsr DWORD PTR [r14+0x2c]
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	40                   	rex
  6f:	41 0f ae 5e 30       	stmxcsr DWORD PTR [r14+0x30]
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	40                   	rex
  78:	41 0f ae 5e 34       	stmxcsr DWORD PTR [r14+0x34]
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	40                   	rex
  81:	41 0f ae 5e 38       	stmxcsr DWORD PTR [r14+0x38]
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	40                   	rex
  8a:	41 0f ae 5e 3c       	stmxcsr DWORD PTR [r14+0x3c]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.13
- Reference cycles: 12.68
- UOPS_EXECUTED.THREAD: 64.16
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 0.48
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.34
- UOPS_PORT_3: 5.67
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 16.11
- UOPS_PORT_7: 6.01
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 0.72
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 3.0
- UOPS_MITE: 3.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 1 NOP

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	90                   	nop

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 1.0
- Reference cycles: 0.62
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 4.0
- UOPS_MITE: 4.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 2 NOPs

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	90                   	nop
   6:	90                   	nop

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 2.0
- Reference cycles: 1.59
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 5.0
- UOPS_MITE: 5.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With unroll_count=500, no inner loop, and 3 NOPs

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	90                   	nop
   6:	90                   	nop
   7:	90                   	nop

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 2.0
- Reference cycles: 1.69
- UOPS_EXECUTED.THREAD: 4.0
- RETIRE_SLOTS: 6.0
- UOPS_MITE: 6.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 2.0

With loop_count=1000 and unroll_count=10

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.1
- Reference cycles: 0.87
- UOPS_EXECUTED.THREAD: 4.11
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 3.11
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.51
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.1
- Reference cycles: 0.86
- UOPS_EXECUTED.THREAD: 4.11
- RETIRE_SLOTS: 3.1
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.49
- UOPS_PORT_3: 0.51
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.1
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.01
- Reference cycles: 0.79
- UOPS_EXECUTED.THREAD: 4.02
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 3.02
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 1.0

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.01
- Reference cycles: 0.8
- UOPS_EXECUTED.THREAD: 4.02
- RETIRE_SLOTS: 3.01
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 1.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 0.5
- UOPS_PORT_3: 0.5
- UOPS_PORT_4: 1.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 1.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
   b:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  11:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 3.08
- UOPS_EXECUTED.THREAD: 16.0
- RETIRE_SLOTS: 12.0
- UOPS_MITE: 12.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.0
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 4.0

With loop_count=1000 and unroll_count=2

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
   b:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  11:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.51
- Reference cycles: 3.55
- UOPS_EXECUTED.THREAD: 16.53
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.23
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.02
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.07

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.51
- Reference cycles: 3.49
- UOPS_EXECUTED.THREAD: 16.53
- RETIRE_SLOTS: 12.5
- UOPS_MITE: 0.01
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.02
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.5
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
   b:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  11:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.06
- Reference cycles: 3.22
- UOPS_EXECUTED.THREAD: 16.08
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 0.12
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.01
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.04

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.06
- Reference cycles: 3.2
- UOPS_EXECUTED.THREAD: 16.08
- RETIRE_SLOTS: 12.05
- UOPS_MITE: 1.06
- UOPS_MS: 0.0
- UOPS_PORT_0: 4.01
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 2.0
- UOPS_PORT_3: 2.01
- UOPS_PORT_4: 4.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 4.05
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.34

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
   b:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  11:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]
  17:	43 0f ae 5c 2e 10    	stmxcsr DWORD PTR [r14+r13*1+0x10]
  1d:	43 0f ae 5c 2e 14    	stmxcsr DWORD PTR [r14+r13*1+0x14]
  23:	43 0f ae 5c 2e 18    	stmxcsr DWORD PTR [r14+r13*1+0x18]
  29:	43 0f ae 5c 2e 1c    	stmxcsr DWORD PTR [r14+r13*1+0x1c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 6.67
- UOPS_EXECUTED.THREAD: 32.0
- RETIRE_SLOTS: 24.0
- UOPS_MITE: 24.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.0
- UOPS_PORT_3: 4.0
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 8.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 8.0

With loop_count=1000 and unroll_count=1

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
   b:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  11:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]
  17:	43 0f ae 5c 2e 10    	stmxcsr DWORD PTR [r14+r13*1+0x10]
  1d:	43 0f ae 5c 2e 14    	stmxcsr DWORD PTR [r14+r13*1+0x14]
  23:	43 0f ae 5c 2e 18    	stmxcsr DWORD PTR [r14+r13*1+0x18]
  29:	43 0f ae 5c 2e 1c    	stmxcsr DWORD PTR [r14+r13*1+0x1c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 9.03
- Reference cycles: 7.08
- UOPS_EXECUTED.THREAD: 33.06
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.45
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.02
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 9.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.14

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	43 0f ae 5c 2e 10    	stmxcsr DWORD PTR [r14+r13*1+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	43 0f ae 5c 2e 14    	stmxcsr DWORD PTR [r14+r13*1+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	43 0f ae 5c 2e 18    	stmxcsr DWORD PTR [r14+r13*1+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	43 0f ae 5c 2e 1c    	stmxcsr DWORD PTR [r14+r13*1+0x1c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 9.03
- Reference cycles: 7.03
- UOPS_EXECUTED.THREAD: 33.06
- RETIRE_SLOTS: 25.0
- UOPS_MITE: 0.03
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 3.99
- UOPS_PORT_3: 4.03
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 9.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.01

With loop_count=100 and unroll_count=10

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
   b:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  11:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]
  17:	43 0f ae 5c 2e 10    	stmxcsr DWORD PTR [r14+r13*1+0x10]
  1d:	43 0f ae 5c 2e 14    	stmxcsr DWORD PTR [r14+r13*1+0x14]
  23:	43 0f ae 5c 2e 18    	stmxcsr DWORD PTR [r14+r13*1+0x18]
  29:	43 0f ae 5c 2e 1c    	stmxcsr DWORD PTR [r14+r13*1+0x1c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.13
- Reference cycles: 6.39
- UOPS_EXECUTED.THREAD: 32.16
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.24
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.02
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 8.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	43 0f ae 5c 2e 10    	stmxcsr DWORD PTR [r14+r13*1+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	43 0f ae 5c 2e 14    	stmxcsr DWORD PTR [r14+r13*1+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	43 0f ae 5c 2e 18    	stmxcsr DWORD PTR [r14+r13*1+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	43 0f ae 5c 2e 1c    	stmxcsr DWORD PTR [r14+r13*1+0x1c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.13
- Reference cycles: 6.39
- UOPS_EXECUTED.THREAD: 32.16
- RETIRE_SLOTS: 24.1
- UOPS_MITE: 0.24
- UOPS_MS: 0.0
- UOPS_PORT_0: 8.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 4.01
- UOPS_PORT_3: 4.02
- UOPS_PORT_4: 8.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 8.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.08

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
   b:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  11:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]
  17:	43 0f ae 5c 2e 10    	stmxcsr DWORD PTR [r14+r13*1+0x10]
  1d:	43 0f ae 5c 2e 14    	stmxcsr DWORD PTR [r14+r13*1+0x14]
  23:	43 0f ae 5c 2e 18    	stmxcsr DWORD PTR [r14+r13*1+0x18]
  29:	43 0f ae 5c 2e 1c    	stmxcsr DWORD PTR [r14+r13*1+0x1c]
  2f:	43 0f ae 5c 2e 20    	stmxcsr DWORD PTR [r14+r13*1+0x20]
  35:	43 0f ae 5c 2e 24    	stmxcsr DWORD PTR [r14+r13*1+0x24]
  3b:	43 0f ae 5c 2e 28    	stmxcsr DWORD PTR [r14+r13*1+0x28]
  41:	43 0f ae 5c 2e 2c    	stmxcsr DWORD PTR [r14+r13*1+0x2c]
  47:	43 0f ae 5c 2e 30    	stmxcsr DWORD PTR [r14+r13*1+0x30]
  4d:	43 0f ae 5c 2e 34    	stmxcsr DWORD PTR [r14+r13*1+0x34]
  53:	43 0f ae 5c 2e 38    	stmxcsr DWORD PTR [r14+r13*1+0x38]
  59:	43 0f ae 5c 2e 3c    	stmxcsr DWORD PTR [r14+r13*1+0x3c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 12.83
- UOPS_EXECUTED.THREAD: 64.0
- RETIRE_SLOTS: 48.0
- UOPS_MITE: 48.0
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.0
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.0
- UOPS_PORT_3: 8.0
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 16.0
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 16.0

With loop_count=1000 and unroll_count=1

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
   b:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  11:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]
  17:	43 0f ae 5c 2e 10    	stmxcsr DWORD PTR [r14+r13*1+0x10]
  1d:	43 0f ae 5c 2e 14    	stmxcsr DWORD PTR [r14+r13*1+0x14]
  23:	43 0f ae 5c 2e 18    	stmxcsr DWORD PTR [r14+r13*1+0x18]
  29:	43 0f ae 5c 2e 1c    	stmxcsr DWORD PTR [r14+r13*1+0x1c]
  2f:	43 0f ae 5c 2e 20    	stmxcsr DWORD PTR [r14+r13*1+0x20]
  35:	43 0f ae 5c 2e 24    	stmxcsr DWORD PTR [r14+r13*1+0x24]
  3b:	43 0f ae 5c 2e 28    	stmxcsr DWORD PTR [r14+r13*1+0x28]
  41:	43 0f ae 5c 2e 2c    	stmxcsr DWORD PTR [r14+r13*1+0x2c]
  47:	43 0f ae 5c 2e 30    	stmxcsr DWORD PTR [r14+r13*1+0x30]
  4d:	43 0f ae 5c 2e 34    	stmxcsr DWORD PTR [r14+r13*1+0x34]
  53:	43 0f ae 5c 2e 38    	stmxcsr DWORD PTR [r14+r13*1+0x38]
  59:	43 0f ae 5c 2e 3c    	stmxcsr DWORD PTR [r14+r13*1+0x3c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 17.03
- Reference cycles: 13.4
- UOPS_EXECUTED.THREAD: 65.06
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 16.07
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 7.91
- UOPS_PORT_3: 8.11
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 17.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 5.02

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	43 0f ae 5c 2e 10    	stmxcsr DWORD PTR [r14+r13*1+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	43 0f ae 5c 2e 14    	stmxcsr DWORD PTR [r14+r13*1+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	43 0f ae 5c 2e 18    	stmxcsr DWORD PTR [r14+r13*1+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	43 0f ae 5c 2e 1c    	stmxcsr DWORD PTR [r14+r13*1+0x1c]
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	43 0f ae 5c 2e 20    	stmxcsr DWORD PTR [r14+r13*1+0x20]
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	43 0f ae 5c 2e 24    	stmxcsr DWORD PTR [r14+r13*1+0x24]
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	43 0f ae 5c 2e 28    	stmxcsr DWORD PTR [r14+r13*1+0x28]
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	43 0f ae 5c 2e 2c    	stmxcsr DWORD PTR [r14+r13*1+0x2c]
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	43 0f ae 5c 2e 30    	stmxcsr DWORD PTR [r14+r13*1+0x30]
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	43 0f ae 5c 2e 34    	stmxcsr DWORD PTR [r14+r13*1+0x34]
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	43 0f ae 5c 2e 38    	stmxcsr DWORD PTR [r14+r13*1+0x38]
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	43 0f ae 5c 2e 3c    	stmxcsr DWORD PTR [r14+r13*1+0x3c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 17.03
- Reference cycles: 13.4
- UOPS_EXECUTED.THREAD: 65.06
- RETIRE_SLOTS: 49.0
- UOPS_MITE: 0.05
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 7.91
- UOPS_PORT_3: 8.11
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 17.01
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.02

With loop_count=100 and unroll_count=10

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
   b:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  11:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]
  17:	43 0f ae 5c 2e 10    	stmxcsr DWORD PTR [r14+r13*1+0x10]
  1d:	43 0f ae 5c 2e 14    	stmxcsr DWORD PTR [r14+r13*1+0x14]
  23:	43 0f ae 5c 2e 18    	stmxcsr DWORD PTR [r14+r13*1+0x18]
  29:	43 0f ae 5c 2e 1c    	stmxcsr DWORD PTR [r14+r13*1+0x1c]
  2f:	43 0f ae 5c 2e 20    	stmxcsr DWORD PTR [r14+r13*1+0x20]
  35:	43 0f ae 5c 2e 24    	stmxcsr DWORD PTR [r14+r13*1+0x24]
  3b:	43 0f ae 5c 2e 28    	stmxcsr DWORD PTR [r14+r13*1+0x28]
  41:	43 0f ae 5c 2e 2c    	stmxcsr DWORD PTR [r14+r13*1+0x2c]
  47:	43 0f ae 5c 2e 30    	stmxcsr DWORD PTR [r14+r13*1+0x30]
  4d:	43 0f ae 5c 2e 34    	stmxcsr DWORD PTR [r14+r13*1+0x34]
  53:	43 0f ae 5c 2e 38    	stmxcsr DWORD PTR [r14+r13*1+0x38]
  59:	43 0f ae 5c 2e 3c    	stmxcsr DWORD PTR [r14+r13*1+0x3c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.13
- Reference cycles: 12.55
- UOPS_EXECUTED.THREAD: 64.16
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 0.48
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.02
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 16.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

Code:

   0:	40                   	rex
   1:	40                   	rex
   2:	40                   	rex
   3:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   8:	40                   	rex
   9:	40                   	rex
   a:	40                   	rex
   b:	43 0f ae 5c 2e 04    	stmxcsr DWORD PTR [r14+r13*1+0x4]
  11:	40                   	rex
  12:	40                   	rex
  13:	40                   	rex
  14:	43 0f ae 5c 2e 08    	stmxcsr DWORD PTR [r14+r13*1+0x8]
  1a:	40                   	rex
  1b:	40                   	rex
  1c:	40                   	rex
  1d:	43 0f ae 5c 2e 0c    	stmxcsr DWORD PTR [r14+r13*1+0xc]
  23:	40                   	rex
  24:	40                   	rex
  25:	40                   	rex
  26:	43 0f ae 5c 2e 10    	stmxcsr DWORD PTR [r14+r13*1+0x10]
  2c:	40                   	rex
  2d:	40                   	rex
  2e:	40                   	rex
  2f:	43 0f ae 5c 2e 14    	stmxcsr DWORD PTR [r14+r13*1+0x14]
  35:	40                   	rex
  36:	40                   	rex
  37:	40                   	rex
  38:	43 0f ae 5c 2e 18    	stmxcsr DWORD PTR [r14+r13*1+0x18]
  3e:	40                   	rex
  3f:	40                   	rex
  40:	40                   	rex
  41:	43 0f ae 5c 2e 1c    	stmxcsr DWORD PTR [r14+r13*1+0x1c]
  47:	40                   	rex
  48:	40                   	rex
  49:	40                   	rex
  4a:	43 0f ae 5c 2e 20    	stmxcsr DWORD PTR [r14+r13*1+0x20]
  50:	40                   	rex
  51:	40                   	rex
  52:	40                   	rex
  53:	43 0f ae 5c 2e 24    	stmxcsr DWORD PTR [r14+r13*1+0x24]
  59:	40                   	rex
  5a:	40                   	rex
  5b:	40                   	rex
  5c:	43 0f ae 5c 2e 28    	stmxcsr DWORD PTR [r14+r13*1+0x28]
  62:	40                   	rex
  63:	40                   	rex
  64:	40                   	rex
  65:	43 0f ae 5c 2e 2c    	stmxcsr DWORD PTR [r14+r13*1+0x2c]
  6b:	40                   	rex
  6c:	40                   	rex
  6d:	40                   	rex
  6e:	43 0f ae 5c 2e 30    	stmxcsr DWORD PTR [r14+r13*1+0x30]
  74:	40                   	rex
  75:	40                   	rex
  76:	40                   	rex
  77:	43 0f ae 5c 2e 34    	stmxcsr DWORD PTR [r14+r13*1+0x34]
  7d:	40                   	rex
  7e:	40                   	rex
  7f:	40                   	rex
  80:	43 0f ae 5c 2e 38    	stmxcsr DWORD PTR [r14+r13*1+0x38]
  86:	40                   	rex
  87:	40                   	rex
  88:	40                   	rex
  89:	43 0f ae 5c 2e 3c    	stmxcsr DWORD PTR [r14+r13*1+0x3c]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.13
- Reference cycles: 12.76
- UOPS_EXECUTED.THREAD: 64.16
- RETIRE_SLOTS: 48.1
- UOPS_MITE: 0.48
- UOPS_MS: 0.0
- UOPS_PORT_0: 16.03
- UOPS_PORT_1: 0.0
- UOPS_PORT_2: 8.02
- UOPS_PORT_3: 8.01
- UOPS_PORT_4: 16.0
- UOPS_PORT_5: 0.0
- UOPS_PORT_6: 16.11
- UOPS_PORT_7: 0.0
- DIV_CYCLES: 0.0
- ILD_STALL.LCP: 0.0
- UOPS_MITE>=1: 0.16

STMXCSR (M32) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With unroll_count=500, no inner loop, and 1 NOP

With unroll_count=500, no inner loop, and 2 NOPs

With unroll_count=500, no inner loop, and 3 NOPs

With loop_count=1000 and unroll_count=10

With loop_count=1000, unroll_count=10, and padding (redundant prefixes)

With loop_count=100 and unroll_count=100

With loop_count=100, unroll_count=100, and padding (redundant prefixes)

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=1000, unroll_count=2, and padding (redundant prefixes)

With loop_count=100 and unroll_count=20

With loop_count=100, unroll_count=20, and padding (redundant prefixes)

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=1000, unroll_count=1, and padding (redundant prefixes)

With loop_count=100 and unroll_count=10

With loop_count=100, unroll_count=10, and padding (redundant prefixes)