STMXCSR (M32) - Port Usage

With blocking instructions for port '0':

Code:

   0:	66 0f 38 de c1       	aesdec xmm0,xmm1
   5:	66 0f 38 de d1       	aesdec xmm2,xmm1
   a:	66 0f 38 de d9       	aesdec xmm3,xmm1
   f:	66 0f 38 de e1       	aesdec xmm4,xmm1
  14:	66 0f 38 de e9       	aesdec xmm5,xmm1
  19:	66 0f 38 de f1       	aesdec xmm6,xmm1
  1e:	66 0f 38 de f9       	aesdec xmm7,xmm1
  23:	66 44 0f 38 de c1    	aesdec xmm8,xmm1
  29:	66 44 0f 38 de c9    	aesdec xmm9,xmm1
  2f:	66 44 0f 38 de d1    	aesdec xmm10,xmm1
  35:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.1
- Reference cycles: 9.75
- UOPS_PORT_0: 11.0

⇨ One μop that can only use port '0'

With blocking instructions for port '4':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.09
- Reference cycles: 9.75
- UOPS_PORT_4: 11.0

⇨ One μop that can only use port '4'

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 6.14
- Reference cycles: 5.5
- UOPS_PORT_0: 5.93
- UOPS_PORT_6: 6.07

⇨ One μop that can only use ports {'0', '6'}

With blocking instructions for ports {'2', '3', '7'}:

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	4d 89 86 90 00 00 00 	mov    QWORD PTR [r14+0x90],r8
  35:	4d 89 86 98 00 00 00 	mov    QWORD PTR [r14+0x98],r8
  3c:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]

Init:
```
VZEROALL
```
Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 13.11
- Reference cycles: 11.45
- UOPS_PORT_7: 4.51
- UOPS_PORT_3: 4.7
- UOPS_PORT_2: 3.78

⇨ One μop that can only use ports {'2', '3', '7'}

With an indexed addressing mode

With blocking instructions for port '0':

Code:

   0:	66 0f 38 de c1       	aesdec xmm0,xmm1
   5:	66 0f 38 de d1       	aesdec xmm2,xmm1
   a:	66 0f 38 de d9       	aesdec xmm3,xmm1
   f:	66 0f 38 de e1       	aesdec xmm4,xmm1
  14:	66 0f 38 de e9       	aesdec xmm5,xmm1
  19:	66 0f 38 de f1       	aesdec xmm6,xmm1
  1e:	66 0f 38 de f9       	aesdec xmm7,xmm1
  23:	66 44 0f 38 de c1    	aesdec xmm8,xmm1
  29:	66 44 0f 38 de c9    	aesdec xmm9,xmm1
  2f:	66 44 0f 38 de d1    	aesdec xmm10,xmm1
  35:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM3, XMM3;
PXOR XMM4, XMM4;
PXOR XMM5, XMM5;
PXOR XMM6, XMM6;
PXOR XMM7, XMM7;
PXOR XMM8, XMM8;
PXOR XMM9, XMM9;
PXOR XMM10, XMM10;
PXOR XMM11, XMM11;
PXOR XMM12, XMM12;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.1
- Reference cycles: 10.0
- UOPS_PORT_0: 11.0

⇨ One μop that can only use port '0'

With blocking instructions for port '4':

Code:

   0:	4d 89 46 40          	mov    QWORD PTR [r14+0x40],r8
   4:	4d 89 46 48          	mov    QWORD PTR [r14+0x48],r8
   8:	4d 89 46 50          	mov    QWORD PTR [r14+0x50],r8
   c:	4d 89 46 58          	mov    QWORD PTR [r14+0x58],r8
  10:	4d 89 46 60          	mov    QWORD PTR [r14+0x60],r8
  14:	4d 89 46 68          	mov    QWORD PTR [r14+0x68],r8
  18:	4d 89 46 70          	mov    QWORD PTR [r14+0x70],r8
  1c:	4d 89 46 78          	mov    QWORD PTR [r14+0x78],r8
  20:	4d 89 86 80 00 00 00 	mov    QWORD PTR [r14+0x80],r8
  27:	4d 89 86 88 00 00 00 	mov    QWORD PTR [r14+0x88],r8
  2e:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 11.09
- Reference cycles: 9.75
- UOPS_PORT_4: 11.0

⇨ One μop that can only use port '4'

With blocking instructions for ports {'0', '6'}:

Code:

   0:	66 41 c1 c0 00       	rol    r8w,0x0
   5:	66 41 c1 c1 00       	rol    r9w,0x0
   a:	66 41 c1 c2 00       	rol    r10w,0x0
   f:	66 41 c1 c3 00       	rol    r11w,0x0
  14:	66 41 c1 c4 00       	rol    r12w,0x0
  19:	66 c1 c3 00          	rol    bx,0x0
  1d:	66 c1 c1 00          	rol    cx,0x0
  21:	66 c1 c2 00          	rol    dx,0x0
  25:	66 41 c1 c0 00       	rol    r8w,0x0
  2a:	66 41 c1 c1 00       	rol    r9w,0x0
  2f:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 6.14
- Reference cycles: 5.5
- UOPS_PORT_0: 5.93
- UOPS_PORT_6: 6.07

⇨ One μop that can only use ports {'0', '6'}

With blocking instructions for ports {'2', '3'}:

Code:

   0:	f2 41 0f f0 46 40    	lddqu  xmm0,[r14+0x40]
   6:	f2 41 0f f0 4e 50    	lddqu  xmm1,[r14+0x50]
   c:	f2 41 0f f0 56 60    	lddqu  xmm2,[r14+0x60]
  12:	f2 41 0f f0 5e 70    	lddqu  xmm3,[r14+0x70]
  18:	f2 41 0f f0 a6 80 00 	lddqu  xmm4,[r14+0x80]
  1f:	00 00 
  21:	f2 41 0f f0 ae 90 00 	lddqu  xmm5,[r14+0x90]
  28:	00 00 
  2a:	f2 41 0f f0 b6 a0 00 	lddqu  xmm6,[r14+0xa0]
  31:	00 00 
  33:	f2 41 0f f0 be b0 00 	lddqu  xmm7,[r14+0xb0]
  3a:	00 00 
  3c:	f2 45 0f f0 86 c0 00 	lddqu  xmm8,[r14+0xc0]
  43:	00 00 
  45:	f2 45 0f f0 8e d0 00 	lddqu  xmm9,[r14+0xd0]
  4c:	00 00 
  4e:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]

Init:
```
VZEROALL;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 5.59
- Reference cycles: 5.0
- UOPS_PORT_3: 5.5
- UOPS_PORT_2: 5.5

⇨ One μop that can only use ports {'2', '3'}