STMXCSR (M32)

Experiment 1

Instruction: STMXCSR dword ptr [R14]
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥7

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 31 e6             	xor    r14,r12
  16:	4d 31 e6             	xor    r14,r12

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 13.97
- Reference cycles: 12.88
- UOPS_RETIRED.ANY: 10.0

Experiment 2 (with additional nop)

Instruction: STMXCSR dword ptr [R14]
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥7

Code:

   0:	41 0f ae 1e          	stmxcsr DWORD PTR [r14]
   4:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 31 e6             	xor    r14,r12
  16:	4d 31 e6             	xor    r14,r12
  19:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 13.98
- Reference cycles: 12.84
- UOPS_RETIRED.ANY: 11.0

Experiment 1

Instruction: STMXCSR dword ptr [R14+R13]
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥7

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 31 e5             	xor    r13,r12
  18:	4d 31 e5             	xor    r13,r12

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 13.99
- Reference cycles: 12.96
- UOPS_RETIRED.ANY: 10.0

Experiment 2 (with additional nop)

Instruction: STMXCSR dword ptr [R14+R13]
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥7

Code:

   0:	43 0f ae 1c 2e       	stmxcsr DWORD PTR [r14+r13*1]
   5:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 31 e5             	xor    r13,r12
  18:	4d 31 e5             	xor    r13,r12
  1b:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 13.98
- Reference cycles: 12.84
- UOPS_RETIRED.ANY: 11.0

STMXCSR (M32) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤7

Latency operand 1 → 1 (address, index register): ≤7

Latency operand 1 → 1 (address, base register): ≤7

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤7

Experiment 1

Experiment 2 (with additional nop)