CMPXCHG_LOCK (M64, R64)

Operands

• Operand 1 (r/w): Memory
• Operand 2 (r): Register (RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, R8, R9, R10, R11, R12, R13, R14, R15)
• Operand 3 (r/w, suppressed): Register (RAX)
• Operand 4 (w, suppressed): Flags (AF: w, CF: w, OF: w, PF: w, SF: w, ZF: w)

Available performance data

• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• Ivy Bridge
• Sandy Bridge
• Westmere
• Nehalem
• Wolfdale
• Conroe
• Tremont
• Goldmont Plus
• Goldmont
• Airmont
• Bonnell
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤43
  • Latency operand 1 → 1 (address, index register): ≤43
  • Latency operand 1 → 1 (memory): 19
  • Latency operand 1 → 3 (address, base register): 14
  • Latency operand 1 → 3 (address, index register): 14
  • Latency operand 1 → 3 (memory): ≤19
  • Latency operand 1 → 4 (address, base register): 18
  • Latency operand 1 → 4 (address, index register): 18
  • Latency operand 1 → 4 (memory): ≤19
  • Latency operand 2 → 1: ≤31
  • Latency operand 2 → 3: 14
  • Latency operand 2 → 4: 14
  • Latency operand 3 → 1: ≤31
  • Latency operand 3 → 3: 14
  • Latency operand 3 → 4: 14
• Throughput
  • Computed from the port usage: 1.80
  • Measured (loop): 19.07
  • Measured (unrolled): 19.04
• Number of μops
  • Executed: 8
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 6*p0156B+3*p06+1*p23A+1*p49+1*p78

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤22
  • Latency operand 1 → 1 (address, index register): ≤22
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 3 (address, base register): 16
  • Latency operand 1 → 3 (address, index register): 16
  • Latency operand 1 → 3 (memory): ≤16
  • Latency operand 1 → 4 (address, base register): 16
  • Latency operand 1 → 4 (address, index register): 16
  • Latency operand 1 → 4 (memory): ≤14
  • Latency operand 2 → 1: ≤20
  • Latency operand 2 → 3: 14
  • Latency operand 2 → 4: 13
  • Latency operand 3 → 1: ≤20
  • Latency operand 3 → 3: 14
  • Latency operand 3 → 4: 13
• Throughput
  • Measured (loop): 18.00
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 7
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤33
  • Latency operand 1 → 1 (address, index register): ≤33
  • Latency operand 1 → 1 (memory): 21
  • Latency operand 1 → 3 (address, base register): 15
  • Latency operand 1 → 3 (address, index register): 15
  • Latency operand 1 → 3 (memory): ≤21
  • Latency operand 1 → 4 (address, base register): 20
  • Latency operand 1 → 4 (address, index register): 20
  • Latency operand 1 → 4 (memory): ≤21
  • Latency operand 2 → 1: ≤33
  • Latency operand 2 → 3: 15
  • Latency operand 2 → 4: 13
  • Latency operand 3 → 1: ≤33
  • Latency operand 3 → 3: 15
  • Latency operand 3 → 4: 13
• Throughput
  • Computed from the port usage: 2.25
  • Measured (loop): 19.06
  • Measured (unrolled): 19.00
• Number of μops
  • Executed: 8
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 6*p0156+3*p06+1*p23+1*p49+1*p78

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤33
  • Latency operand 1 → 1 (address, index register): ≤33
  • Latency operand 1 → 1 (memory): 21
  • Latency operand 1 → 3 (address, base register): 15
  • Latency operand 1 → 3 (address, index register): 15
  • Latency operand 1 → 3 (memory): ≤21
  • Latency operand 1 → 4 (address, base register): 20
  • Latency operand 1 → 4 (address, index register): 20
  • Latency operand 1 → 4 (memory): ≤21
  • Latency operand 2 → 1: ≤33
  • Latency operand 2 → 3: 15
  • Latency operand 2 → 4: 13
  • Latency operand 3 → 1: ≤33
  • Latency operand 3 → 3: 15
  • Latency operand 3 → 4: 13
• Throughput
  • Computed from the port usage: 2.25
  • Measured (loop): 19.00
  • Measured (unrolled): 19.00
• Number of μops
  • Executed: 8
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 6*p0156+3*p06+1*p23+1*p49+1*p78

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤33
  • Latency operand 1 → 1 (address, index register): ≤33
  • Latency operand 1 → 1 (memory): 21
  • Latency operand 1 → 3 (address, base register): 15
  • Latency operand 1 → 3 (address, index register): 15
  • Latency operand 1 → 3 (memory): ≤21
  • Latency operand 1 → 4 (address, base register): 20
  • Latency operand 1 → 4 (address, index register): 20
  • Latency operand 1 → 4 (memory): ≤21
  • Latency operand 2 → 1: ≤33
  • Latency operand 2 → 3: 15
  • Latency operand 2 → 4: 13
  • Latency operand 3 → 1: ≤33
  • Latency operand 3 → 3: 15
  • Latency operand 3 → 4: 13
• Throughput
  • Computed from the port usage: 2.25
  • Measured (loop): 19.06
  • Measured (unrolled): 19.00
• Number of μops
  • Executed: 8
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 6*p0156+3*p06+1*p23+1*p49+1*p78

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤29
  • Latency operand 1 → 1 (address, index register): ≤29
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 3 (address, base register): 14
  • Latency operand 1 → 3 (address, index register): 14
  • Latency operand 1 → 3 (memory): ≤16
  • Latency operand 1 → 4 (address, base register): 17
  • Latency operand 1 → 4 (address, index register): 17
  • Latency operand 1 → 4 (memory): ≤16
  • Latency operand 2 → 1: ≤28
  • Latency operand 2 → 3: 13
  • Latency operand 2 → 4: 13
  • Latency operand 3 → 1: ≤28
  • Latency operand 3 → 3: 13
  • Latency operand 3 → 4: 13
• Throughput
  • Computed from the port usage: 2.25 (if an indexed addressing mode is used: 2.00)
  • Measured (loop): 17.00
  • Measured (unrolled): 17.00
• Number of μops
  • Executed: 9
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+4*p0156+4*p06+2*p23+1*p4 (if an indexed addressing mode is used: 1*p015+3*p0156+4*p06+2*p23+1*p4)

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤29
  • Latency operand 1 → 1 (address, index register): ≤29
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 3 (address, base register): 14
  • Latency operand 1 → 3 (address, index register): 14
  • Latency operand 1 → 3 (memory): ≤16
  • Latency operand 1 → 4 (address, base register): 17
  • Latency operand 1 → 4 (address, index register): 17
  • Latency operand 1 → 4 (memory): ≤15
  • Latency operand 2 → 1: ≤28
  • Latency operand 2 → 3: 13
  • Latency operand 2 → 4: 12
  • Latency operand 3 → 1: ≤28
  • Latency operand 3 → 3: 13
  • Latency operand 3 → 4: 12
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 18.02
  • Measured (unrolled): 18.00
• Number of μops
  • Executed: 8
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 6*p0156+2*p06+2*p23+1*p4

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤29
  • Latency operand 1 → 1 (address, index register): ≤29
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 3 (address, base register): 14
  • Latency operand 1 → 3 (address, index register): 14
  • Latency operand 1 → 3 (memory): ≤16
  • Latency operand 1 → 4 (address, base register): 17
  • Latency operand 1 → 4 (address, index register): 17
  • Latency operand 1 → 4 (memory): ≤15
  • Latency operand 2 → 1: ≤28
  • Latency operand 2 → 3: 13
  • Latency operand 2 → 4: 13
  • Latency operand 3 → 1: ≤28
  • Latency operand 3 → 3: 13
  • Latency operand 3 → 4: 12
• Throughput
  • Computed from the port usage: 2.25
  • Measured (loop): 17.00
  • Measured (unrolled): 17.00
• Number of μops
  • Executed: 9
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+4*p0156+4*p06+2*p23+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.24
• Number of μops: 10
• Port usage: 3*p0156+4*p06+1*p23+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00
• Number of μops: 10
• Port usage: 3*p0156+4*p06+1*p23+1*p237+1*p4

Coffee Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤29
  • Latency operand 1 → 1 (address, index register): ≤29
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 3 (address, base register): 14
  • Latency operand 1 → 3 (address, index register): 14
  • Latency operand 1 → 3 (memory): ≤16
  • Latency operand 1 → 4 (address, base register): 17
  • Latency operand 1 → 4 (address, index register): 17
  • Latency operand 1 → 4 (memory): ≤15
  • Latency operand 2 → 1: ≤28
  • Latency operand 2 → 3: 13
  • Latency operand 2 → 4: 12
  • Latency operand 3 → 1: ≤28
  • Latency operand 3 → 3: 13
  • Latency operand 3 → 4: 12
• Throughput
  • Computed from the port usage: 2.25
  • Measured (loop): 17.00
  • Measured (unrolled): 17.00
• Number of μops
  • Executed: 9
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 5*p0156+4*p06+2*p23+1*p4

Kaby Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤29
  • Latency operand 1 → 1 (address, index register): ≤29
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 3 (address, base register): 14
  • Latency operand 1 → 3 (address, index register): 14
  • Latency operand 1 → 3 (memory): ≤16
  • Latency operand 1 → 4 (address, base register): 17
  • Latency operand 1 → 4 (address, index register): 17
  • Latency operand 1 → 4 (memory): ≤15
  • Latency operand 2 → 1: ≤28
  • Latency operand 2 → 3: 13
  • Latency operand 2 → 4: 13
  • Latency operand 3 → 1: ≤28
  • Latency operand 3 → 3: 13
  • Latency operand 3 → 4: 12
• Throughput
  • Computed from the port usage: 2.25
  • Measured (loop): 17.00
  • Measured (unrolled): 17.00
• Number of μops
  • Executed: 9
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 5*p0156+4*p06+2*p23+1*p4

Skylake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤29
  • Latency operand 1 → 1 (address, index register): ≤29
  • Latency operand 1 → 1 (memory): 18
  • Latency operand 1 → 3 (address, base register): 14
  • Latency operand 1 → 3 (address, index register): 14
  • Latency operand 1 → 3 (memory): ≤16
  • Latency operand 1 → 4 (address, base register): 17
  • Latency operand 1 → 4 (address, index register): 17
  • Latency operand 1 → 4 (memory): ≤15
  • Latency operand 2 → 1: ≤28
  • Latency operand 2 → 3: 13
  • Latency operand 2 → 4: 12
  • Latency operand 3 → 1: ≤28
  • Latency operand 3 → 3: 13
  • Latency operand 3 → 4: 12
• Throughput
  • Computed from the port usage: 2.25
  • Measured (loop): 17.00
  • Measured (unrolled): 17.00
• Number of μops
  • Executed: 9
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 5*p0156+4*p06+2*p23+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.24
• Number of μops: 10
• Port usage: 3*p0156+4*p06+1*p23+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00
• Number of μops: 10
• Port usage: 3*p0156+4*p06+1*p23+1*p237+1*p4

Broadwell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤32
  • Latency operand 1 → 1 (address, index register): ≤32
  • Latency operand 1 → 1 (memory): 21
  • Latency operand 1 → 3 (address, base register): 14
  • Latency operand 1 → 3 (address, index register): 14
  • Latency operand 1 → 3 (memory): ≤18
  • Latency operand 1 → 4 (address, base register): 20
  • Latency operand 1 → 4 (address, index register): 20
  • Latency operand 1 → 4 (memory): ≤17
  • Latency operand 2 → 1: ≤31
  • Latency operand 2 → 3: 14
  • Latency operand 2 → 4: 12
  • Latency operand 3 → 1: ≤31
  • Latency operand 3 → 3: 14
  • Latency operand 3 → 4: 12
• Throughput
  • Computed from the port usage: 2.25
  • Measured (loop): 21.00
  • Measured (unrolled): 21.00
• Number of μops
  • Executed: 9
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 5*p0156+4*p06+2*p23+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.25 (with the -no_interiteration flag: 5.24)
• Number of μops: 10
• Port usage: 3*p0156+4*p06+1*p23+1*p237+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.24
• Number of μops: 10
• Port usage: 3*p0156+4*p06+1*p23+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00
• Number of μops: 10
• Port usage: 3*p0156+4*p06+1*p23+1*p237+1*p4

Haswell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤30
  • Latency operand 1 → 1 (address, index register): ≤30
  • Latency operand 1 → 1 (memory): 19
  • Latency operand 1 → 3 (address, base register): 14
  • Latency operand 1 → 3 (address, index register): 14
  • Latency operand 1 → 3 (memory): ≤17
  • Latency operand 1 → 4 (address, base register): 17
  • Latency operand 1 → 4 (address, index register): 17
  • Latency operand 1 → 4 (memory): ≤16
  • Latency operand 2 → 1: ≤29
  • Latency operand 2 → 3: 13
  • Latency operand 2 → 4: 13
  • Latency operand 3 → 1: ≤29
  • Latency operand 3 → 3: 13
  • Latency operand 3 → 4: 13
• Throughput
  • Computed from the port usage: 2.25
  • Measured (loop): 19.00
  • Measured (unrolled): 19.00
• Number of μops
  • Executed: 9
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 5*p0156+4*p06+2*p23+1*p4
• IACA 2.1
• Latency: 8
• Throughput
  • Computed from the port usage: 0.75
  • IACA: 1.00 (with the -no_interiteration flag: 0.75)
• Number of μops: 4
• Port usage: 3*p0156+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.25 (with the -no_interiteration flag: 4.90)
• Number of μops: 10
• Port usage: 3*p0156+4*p06+1*p23+1*p237+1*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.24
• Number of μops: 10
• Port usage: 3*p0156+4*p06+1*p23+1*p237+1*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 2.00
  • IACA: 2.00
• Number of μops: 10
• Port usage: 3*p0156+4*p06+1*p23+1*p237+1*p4

Ivy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤33
  • Latency operand 1 → 1 (address, index register): ≤33
  • Latency operand 1 → 1 (memory): 22
  • Latency operand 1 → 3 (address, base register): 14
  • Latency operand 1 → 3 (address, index register): 14
  • Latency operand 1 → 3 (memory): ≤17
  • Latency operand 1 → 4 (address, base register): 20
  • Latency operand 1 → 4 (address, index register): 20
  • Latency operand 1 → 4 (memory): ≤16
  • Latency operand 2 → 1: ≤32
  • Latency operand 2 → 3: 13
  • Latency operand 2 → 4: 12
  • Latency operand 3 → 1: ≤32
  • Latency operand 3 → 3: 13
  • Latency operand 3 → 4: 12
• Throughput
  • Computed from the port usage: 2.67
  • Measured (loop): 22.00
  • Measured (unrolled): 22.00
• Number of μops
  • Executed: 9
  • Retire slots: 9
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 9
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 6*p015+2*p23+1*p4+2*p5
• IACA 2.1
• Latency: 8
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 3*p015+1*p23

Sandy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤34
  • Latency operand 1 → 1 (address, index register): ≤34
  • Latency operand 1 → 1 (memory): 23
  • Latency operand 1 → 3 (address, base register): 14
  • Latency operand 1 → 3 (address, index register): 14
  • Latency operand 1 → 3 (memory): ≤18
  • Latency operand 1 → 4 (address, base register): 21
  • Latency operand 1 → 4 (address, index register): 21
  • Latency operand 1 → 4 (memory): ≤18
  • Latency operand 2 → 1: ≤33
  • Latency operand 2 → 3: 13
  • Latency operand 2 → 4: 13
  • Latency operand 3 → 1: ≤33
  • Latency operand 3 → 3: 13
  • Latency operand 3 → 4: 13
• Throughput
  • Computed from the port usage: 3.67 (if an indexed addressing mode is used: 3.33)
  • Measured (loop): 23.00
  • Measured (unrolled): 23.00
• Number of μops
  • Executed: 10
  • Retire slots: 10
  • Decoded (MITE): 0
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 8*p015+1*p1+2*p23+1*p4+2*p5 (if an indexed addressing mode is used: 7*p015+1*p1+2*p23+1*p4+2*p5)
• IACA 2.1
• Latency: 8
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 3*p015+1*p23

Westmere

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤28
  • Latency operand 1 → 1 (address, index register): ≤28
  • Latency operand 1 → 1 (memory): 19
  • Latency operand 1 → 3 (address, base register): 12
  • Latency operand 1 → 3 (address, index register): 12
  • Latency operand 1 → 3 (memory): ≤16
  • Latency operand 1 → 4 (address, base register): 17
  • Latency operand 1 → 4 (address, index register): 17
  • Latency operand 1 → 4 (memory): ≤16
  • Latency operand 2 → 1: ≤27
  • Latency operand 2 → 3: 11
  • Latency operand 2 → 4: 11
  • Latency operand 3 → 1: ≤27
  • Latency operand 3 → 3: 11
  • Latency operand 3 → 4: 11
• Throughput
  • Computed from the port usage: 1.33
  • Measured (loop): 19.00
  • Measured (unrolled): 19.00
• Number of μops
  • Executed: 7
  • Retire slots: 7
  • Microcode Sequencer (MS): 22
  • Requires the complex decoder
• Port usage: 3*p015+1*p05+1*p2+1*p3+1*p4
• IACA 2.1
• Latency: 7
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.33 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p015+2*p05+1*p2

Nehalem

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤28
  • Latency operand 1 → 1 (address, index register): ≤28
  • Latency operand 1 → 1 (memory): 20
  • Latency operand 1 → 3 (address, base register): 12
  • Latency operand 1 → 3 (address, index register): 12
  • Latency operand 1 → 3 (memory): ≤17
  • Latency operand 1 → 4 (address, base register): 19
  • Latency operand 1 → 4 (address, index register): 19
  • Latency operand 1 → 4 (memory): ≤17
  • Latency operand 2 → 1: ≤27
  • Latency operand 2 → 3: 11
  • Latency operand 2 → 4: 11
  • Latency operand 3 → 1: ≤27
  • Latency operand 3 → 3: 11
  • Latency operand 3 → 4: 11
• Throughput
  • Computed from the port usage: 1.33
  • Measured (loop): 20.00
  • Measured (unrolled): 20.00
• Number of μops
  • Executed: 7
  • Retire slots: 7
  • Microcode Sequencer (MS): 22
  • Requires the complex decoder
• Port usage: 3*p015+1*p05+1*p2+1*p3+1*p4
• IACA 2.1
• Latency: 7
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.33 (with the -no_interiteration flag: 1.00)
• Number of μops: 4
• Port usage: 1*p015+2*p05+1*p2

Wolfdale

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤33
  • Latency operand 1 → 1 (address, index register): ≤33
  • Latency operand 1 → 1 (memory): 24
  • Latency operand 1 → 3 (address, base register): 18
  • Latency operand 1 → 3 (address, index register): 18
  • Latency operand 1 → 3 (memory): ≤18
  • Latency operand 1 → 4 (address, base register): 22
  • Latency operand 1 → 4 (address, index register): 22
  • Latency operand 1 → 4 (memory): ≤15
  • Latency operand 2 → 1: ≤33
  • Latency operand 2 → 3: 17
  • Latency operand 2 → 4: 13
  • Latency operand 3 → 1: ≤33
  • Latency operand 3 → 3: 17
  • Latency operand 3 → 4: 13
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 24.20
  • Measured (unrolled): 24.60
• Number of μops
  • Executed: 11
• Port usage: 2*p0+3*p015+1*p2+2*p3+1*p4+1*p5

Conroe

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤33
  • Latency operand 1 → 1 (address, index register): ≤33
  • Latency operand 1 → 1 (memory): 24
  • Latency operand 1 → 3 (address, base register): 18
  • Latency operand 1 → 3 (address, index register): 18
  • Latency operand 1 → 3 (memory): ≤18
  • Latency operand 1 → 4 (address, base register): 22
  • Latency operand 1 → 4 (address, index register): 22
  • Latency operand 1 → 4 (memory): ≤14
  • Latency operand 2 → 1: ≤33
  • Latency operand 2 → 3: 17
  • Latency operand 2 → 4: 13
  • Latency operand 3 → 1: ≤33
  • Latency operand 3 → 3: 17
  • Latency operand 3 → 4: 13
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 24.00
  • Measured (unrolled): 24.00
• Number of μops
  • Executed: 11
• Port usage: 2*p0+4*p015+1*p2+2*p3+1*p4

Tremont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤31
  • Latency operand 1 → 1 (address, index register): ≤31
  • Latency operand 1 → 1 (memory): 15
  • Latency operand 1 → 3 (address, base register): 16
  • Latency operand 1 → 3 (address, index register): 16
  • Latency operand 1 → 3 (memory): ≤15
  • Latency operand 1 → 4 (address, base register): 15
  • Latency operand 1 → 4 (address, index register): 15
  • Latency operand 1 → 4 (memory): ≤14
  • Latency operand 2 → 1: ≤18
  • Latency operand 2 → 3: 15
  • Latency operand 2 → 4: 14
  • Latency operand 3 → 1: ≤18
  • Latency operand 3 → 3: 15
  • Latency operand 3 → 4: 14
• Throughput
  • Measured (loop): 16.04
  • Measured (unrolled): 16.03
• Number of μops
  • Executed: 7
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder

Goldmont Plus

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤42
  • Latency operand 1 → 1 (address, index register): ≤42
  • Latency operand 1 → 1 (memory): 14
  • Latency operand 1 → 3 (address, base register): 15
  • Latency operand 1 → 3 (address, index register): 15
  • Latency operand 1 → 3 (memory): ≤16
  • Latency operand 1 → 4 (address, base register): 14
  • Latency operand 1 → 4 (address, index register): 14
  • Latency operand 1 → 4 (memory): ≤15
  • Latency operand 2 → 1: ≤40
  • Latency operand 2 → 3: 14
  • Latency operand 2 → 4: 14
  • Latency operand 3 → 1: ≤40
  • Latency operand 3 → 3: 14
  • Latency operand 3 → 4: 14
• Throughput
  • Measured (loop): 14.09
  • Measured (unrolled): 14.00
• Number of μops
  • Executed: 8
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder

Goldmont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤19
  • Latency operand 1 → 1 (address, index register): ≤19
  • Latency operand 1 → 1 (memory): 13
  • Latency operand 1 → 3 (address, base register): 16
  • Latency operand 1 → 3 (address, index register): 16
  • Latency operand 1 → 3 (memory): ≤16
  • Latency operand 1 → 4 (address, base register): 14
  • Latency operand 1 → 4 (address, index register): 14
  • Latency operand 1 → 4 (memory): ≤14
  • Latency operand 2 → 1: ≤18
  • Latency operand 2 → 3: 16
  • Latency operand 2 → 4: 14
  • Latency operand 3 → 1: ≤17
  • Latency operand 3 → 3: 14
  • Latency operand 3 → 4: 14
• Throughput
  • Measured (loop): 14.17
  • Measured (unrolled): 14.25
• Number of μops
  • Executed: 8
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder

Airmont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤15
  • Latency operand 1 → 1 (address, index register): ≤15
  • Latency operand 1 → 1 (memory): 12
  • Latency operand 1 → 3 (address, base register): 13
  • Latency operand 1 → 3 (address, index register): 13
  • Latency operand 1 → 3 (memory): ≤11
  • Latency operand 1 → 4 (address, base register): 12
  • Latency operand 1 → 4 (address, index register): 12
  • Latency operand 1 → 4 (memory): ≤12
  • Latency operand 2 → 1: ≤11
  • Latency operand 2 → 3: 12
  • Latency operand 2 → 4: 10
  • Latency operand 3 → 1: ≤11
  • Latency operand 3 → 3: 12
  • Latency operand 3 → 4: 11
• Throughput
  • Measured (loop): 11.57
  • Measured (unrolled): 11.71
• Number of μops
  • Executed: 6
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder

Bonnell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤17
  • Latency operand 1 → 1 (address, index register): ≤17
  • Latency operand 1 → 1 (memory): 21
  • Latency operand 1 → 3 (address, base register): 18
  • Latency operand 1 → 3 (address, index register): 18
  • Latency operand 1 → 3 (memory): ≤22
  • Latency operand 1 → 4 (address, base register): 18
  • Latency operand 1 → 4 (address, index register): 18
  • Latency operand 1 → 4 (memory): ≤22
  • Latency operand 2 → 1: ≤14
  • Latency operand 2 → 3: 15
  • Latency operand 2 → 4: 15
  • Latency operand 3 → 1: ≤15
  • Latency operand 3 → 3: 15
  • Latency operand 3 → 4: 15
• Throughput
  • Measured (loop): 14.02
  • Measured (unrolled): 14.00
• Number of μops
  • Executed: 7
  • Microcode Sequencer (MS): 7
  • Requires the complex decoder

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 8
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 7
  • Latency operand 1 → 3 (memory): ≤9
  • Latency operand 1 → 4 (address, base register): 12
  • Latency operand 1 → 4 (address, index register): 5
  • Latency operand 1 → 4 (memory): ≤7
  • Latency operand 2 → 1: ≤7
  • Latency operand 2 → 3: 0
  • Latency operand 2 → 4: 0
  • Latency operand 3 → 1: ≤8
  • Latency operand 3 → 3: 3
  • Latency operand 3 → 4: 1
• Throughput
  • Measured (loop): 7.94
  • Measured (unrolled): 7.89
• Number of μops
  • Executed: 6

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 8
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 7
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 1 → 4 (address, base register): 12
  • Latency operand 1 → 4 (address, index register): 5
  • Latency operand 1 → 4 (memory): ≤6
  • Latency operand 2 → 1: ≤6
  • Latency operand 2 → 3: 0
  • Latency operand 2 → 4: 0
  • Latency operand 3 → 1: ≤7
  • Latency operand 3 → 3: 3
  • Latency operand 3 → 4: 1
• Throughput
  • Measured (loop): 7.77
  • Measured (unrolled): 7.73
• Number of μops
  • Executed: 6

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤16
  • Latency operand 1 → 1 (address, index register): ≤16
  • Latency operand 1 → 1 (memory): 16
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤9
  • Latency operand 1 → 4 (address, base register): 16
  • Latency operand 1 → 4 (address, index register): 16
  • Latency operand 1 → 4 (memory): ≤9
  • Latency operand 2 → 1: ≤8
  • Latency operand 2 → 3: 0
  • Latency operand 2 → 4: 0
  • Latency operand 3 → 1: ≤9
  • Latency operand 3 → 3: 2
  • Latency operand 3 → 4: 1
• Throughput
  • Measured (loop): 17.35
  • Measured (unrolled): 17.35
• Number of μops
  • Executed: 6

AMD Zen+

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 9
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 7
  • Latency operand 1 → 3 (memory): ≤9
  • Latency operand 1 → 4 (address, base register): 27
  • Latency operand 1 → 4 (address, index register): 27
  • Latency operand 1 → 4 (memory): ≤7
  • Latency operand 2 → 1: ≤7
  • Latency operand 2 → 3: 0
  • Latency operand 2 → 4: 0
  • Latency operand 3 → 1: ≤8
  • Latency operand 3 → 3: 2
  • Latency operand 3 → 4: 1
• Throughput
  • Measured (loop): 27.90
  • Measured (unrolled): 27.90
• Number of μops
  • Executed: 6