CMPXCHG_LOCK (M64, R64) - Throughput and Uops (IACA 2.1)
With a non-indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 3.00 Cycles Throughput Bottleneck: InterIteration
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 1.0 | 1.0 1.0 | 0.0 0.0 | 0.0 | 1.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14], r8
Total Num Of Uops: 4
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 1.35 Cycles Throughput Bottleneck: Port0, Port1, Port5
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 1.3 0.0 | 1.4 | 1.0 1.0 | 0.0 0.0 | 0.0 | 1.4 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4^ | 1.3 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
Total Num Of Uops: 5
With 16 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 48.00 Cycles Throughput Bottleneck: InterIteration
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 16.0 0.0 | 16.0 | 16.0 16.0 | 0.0 0.0 | 0.0 | 16.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x8], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x10], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x18], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x20], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x28], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x30], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x38], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x40], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x48], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x50], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x58], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x60], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x68], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x70], r8
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+0x78], r8
Total Num Of Uops: 64
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 21.35 Cycles Throughput Bottleneck: Port0, Port1, Port5
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 21.4 0.0 | 21.3 | 16.0 16.0 | 0.0 0.0 | 0.0 | 21.4 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4^ | 1.4 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.3 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+0x8], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.4 | 0.3 | 1.0 1.0 | | | 1.3 | CP | lock cmpxchg qword ptr [r14+0x10], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.4 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+0x18], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.3 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+0x20], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.4 | 0.3 | 1.0 1.0 | | | 1.3 | CP | lock cmpxchg qword ptr [r14+0x28], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.4 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+0x30], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.3 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+0x38], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.4 | 0.3 | 1.0 1.0 | | | 1.3 | CP | lock cmpxchg qword ptr [r14+0x40], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.4 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+0x48], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.3 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+0x50], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.4 | 0.3 | 1.0 1.0 | | | 1.3 | CP | lock cmpxchg qword ptr [r14+0x58], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.4 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+0x60], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.3 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+0x68], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.4 | 0.3 | 1.0 1.0 | | | 1.3 | CP | lock cmpxchg qword ptr [r14+0x70], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4^ | 1.4 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+0x78], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
Total Num Of Uops: 80
With an indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 3.00 Cycles Throughput Bottleneck: InterIteration
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 1.0 | 1.0 1.0 | 0.0 0.0 | 0.0 | 1.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1], r8
Total Num Of Uops: 4
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 1.40 Cycles Throughput Bottleneck: Port1, Port5
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 1.2 0.0 | 1.4 | 1.0 1.0 | 0.0 0.0 | 0.0 | 1.4 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4 | 1.2 | 0.4 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+r13*1], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
Total Num Of Uops: 5
With 16 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 48.00 Cycles Throughput Bottleneck: InterIteration
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 16.0 0.0 | 16.0 | 16.0 16.0 | 0.0 0.0 | 0.0 | 16.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x8], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x10], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x18], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x20], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x28], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x30], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x38], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x40], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x48], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x50], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x58], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x60], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x68], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x70], r8
| 4 | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14+r13*1+0x78], r8
Total Num Of Uops: 64
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 21.35 Cycles Throughput Bottleneck: Port0, Port1, Port5
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 21.3 0.0 | 21.4 | 16.0 16.0 | 0.0 0.0 | 0.0 | 21.4 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4 | 1.3 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+r13*1], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.4 | 0.3 | 1.0 1.0 | | | 1.3 | CP | lock cmpxchg qword ptr [r14+r13*1+0x8], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.4 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+r13*1+0x10], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.3 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+r13*1+0x18], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.4 | 0.3 | 1.0 1.0 | | | 1.3 | CP | lock cmpxchg qword ptr [r14+r13*1+0x20], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.4 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+r13*1+0x28], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.3 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+r13*1+0x30], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.4 | 0.3 | 1.0 1.0 | | | 1.3 | CP | lock cmpxchg qword ptr [r14+r13*1+0x38], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.4 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+r13*1+0x40], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.3 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+r13*1+0x48], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.4 | 0.3 | 1.0 1.0 | | | 1.3 | CP | lock cmpxchg qword ptr [r14+r13*1+0x50], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.4 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+r13*1+0x58], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.3 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+r13*1+0x60], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.4 | 0.3 | 1.0 1.0 | | | 1.3 | CP | lock cmpxchg qword ptr [r14+r13*1+0x68], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.4 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+r13*1+0x70], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
| 4 | 1.3 | 0.3 | 1.0 1.0 | | | 1.4 | CP | lock cmpxchg qword ptr [r14+r13*1+0x78], r8
| 1 | | 1.0 | | | | | CP | xor rax, rax
Total Num Of Uops: 80
With the -no_interiteration flag
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: Port0, Port1, PORT2_AGU, Port2_DATA, Port5
Port Binding In Cycles Per Iteration:
-------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 |
-------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 1.0 | 1.0 1.0 | 0.0 0.0 | 0.0 | 1.0 |
-------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | |
---------------------------------------------------------------------
| 4^ | 1.0 | 1.0 | 1.0 1.0 | | | 1.0 | CP | lock cmpxchg qword ptr [r14], r8
Total Num Of Uops: 4