CMPXCHG_LOCK (M64, R64) - Throughput and Uops (IACA 3.0)
With a non-indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 2.00 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 2.0 0.0 | 1.5 | 0.7 0.7 | 0.6 0.6 | 1.0 | 1.5 | 2.0 | 0.7 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 10^ | 2.0 | 1.5 | 0.7 0.7 | 0.6 0.6 | 1.0 | 1.5 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14], r8
Total Num Of Uops: 10
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 2.24 Cycles Throughput Bottleneck: Dependency chains
Loop Count: 24
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 2.0 0.0 | 1.0 | 0.7 0.7 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.7 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14], r8
| 1* | | | | | | | | | xor rax, rax
Total Num Of Uops: 11
With 16 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 32.00 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 32.0 0.0 | 24.0 | 10.7 10.7 | 10.6 10.6 | 16.0 | 24.0 | 32.0 | 10.7 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.6 0.6 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14], r8
| 10^ | 2.0 | 2.0 | 0.6 0.6 | 0.7 0.7 | 1.0 | 1.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x8], r8
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.6 | lock cmpxchg qword ptr [r14+0x10], r8
| 10^ | 2.0 | 2.0 | 0.7 0.7 | 0.6 0.6 | 1.0 | 1.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x18], r8
| 10^ | 2.0 | 1.0 | 0.6 0.6 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x20], r8
| 10^ | 2.0 | 2.0 | 0.7 0.7 | 0.7 0.7 | 1.0 | 1.0 | 2.0 | 0.6 | lock cmpxchg qword ptr [r14+0x28], r8
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.6 0.6 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x30], r8
| 10^ | 2.0 | 2.0 | 0.6 0.6 | 0.7 0.7 | 1.0 | 1.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x38], r8
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.6 | lock cmpxchg qword ptr [r14+0x40], r8
| 10^ | 2.0 | 2.0 | 0.7 0.7 | 0.6 0.6 | 1.0 | 1.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x48], r8
| 10^ | 2.0 | 1.0 | 0.6 0.6 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x50], r8
| 10^ | 2.0 | 2.0 | 0.7 0.7 | 0.7 0.7 | 1.0 | 1.0 | 2.0 | 0.6 | lock cmpxchg qword ptr [r14+0x58], r8
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.6 0.6 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x60], r8
| 10^ | 2.0 | 2.0 | 0.6 0.6 | 0.7 0.7 | 1.0 | 1.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x68], r8
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.6 | lock cmpxchg qword ptr [r14+0x70], r8
| 10^ | 2.0 | 2.0 | 0.7 0.7 | 0.6 0.6 | 1.0 | 1.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x78], r8
Total Num Of Uops: 160
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 36.00 Cycles Throughput Bottleneck: FrontEnd
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 32.0 0.0 | 16.0 | 10.7 10.7 | 10.6 10.6 | 16.0 | 32.0 | 32.0 | 10.7 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.6 0.6 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.6 0.6 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x8], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.6 | lock cmpxchg qword ptr [r14+0x10], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.6 0.6 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x18], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.6 0.6 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x20], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.6 | lock cmpxchg qword ptr [r14+0x28], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.6 0.6 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x30], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.6 0.6 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x38], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.6 | lock cmpxchg qword ptr [r14+0x40], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.6 0.6 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x48], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.6 0.6 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x50], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.6 | lock cmpxchg qword ptr [r14+0x58], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.6 0.6 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x60], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.6 0.6 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x68], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.7 0.7 | 1.0 | 2.0 | 2.0 | 0.6 | lock cmpxchg qword ptr [r14+0x70], r8
| 1* | | | | | | | | | xor rax, rax
| 10^ | 2.0 | 1.0 | 0.7 0.7 | 0.6 0.6 | 1.0 | 2.0 | 2.0 | 0.7 | lock cmpxchg qword ptr [r14+0x78], r8
| 1* | | | | | | | | | xor rax, rax
Total Num Of Uops: 176
With an indexed addressing mode
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 2.48 Cycles Throughput Bottleneck: Dependency chains
Loop Count: 32
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 2.0 0.0 | 1.5 | 1.0 1.0 | 1.0 1.0 | 1.0 | 1.5 | 2.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 10 | 2.0 | 1.5 | 1.0 1.0 | 1.0 1.0 | 1.0 | 1.5 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1], r8
Total Num Of Uops: 10
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 2.74 Cycles Throughput Bottleneck: Dependency chains
Loop Count: 26
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 2.0 0.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1], r8
| 1* | | | | | | | | | xor rax, rax
Total Num Of Uops: 11
With 16 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 39.95 Cycles Throughput Bottleneck: FrontEnd
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 32.0 0.0 | 24.0 | 16.0 16.0 | 16.0 16.0 | 16.0 | 24.0 | 32.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1], r8
| 10 | 2.0 | 2.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x8], r8
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x10], r8
| 10 | 2.0 | 2.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x18], r8
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x20], r8
| 10 | 2.0 | 2.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x28], r8
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x30], r8
| 10 | 2.0 | 2.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x38], r8
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x40], r8
| 10 | 2.0 | 2.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x48], r8
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x50], r8
| 10 | 2.0 | 2.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x58], r8
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x60], r8
| 10 | 2.0 | 2.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x68], r8
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x70], r8
| 10 | 2.0 | 2.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 1.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x78], r8
Total Num Of Uops: 160
With additional dependency-breaking instructions
Throughput Analysis Report
--------------------------
Block Throughput: 43.95 Cycles Throughput Bottleneck: FrontEnd
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 32.0 0.0 | 16.0 | 16.0 16.0 | 16.0 16.0 | 16.0 | 32.0 | 32.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x8], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x10], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x18], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x20], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x28], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x30], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x38], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x40], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x48], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x50], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x58], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x60], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x68], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x70], r8
| 1* | | | | | | | | | xor rax, rax
| 10 | 2.0 | 1.0 | 1.0 1.0 | 1.0 1.0 | 1.0 | 2.0 | 2.0 | | lock cmpxchg qword ptr [r14+r13*1+0x78], r8
| 1* | | | | | | | | | xor rax, rax
Total Num Of Uops: 176