CMPXCHG_LOCK (M64, R64) - Latency


Operands


Latency operand 1 → 1 (address, base register): ≤16

Latency operand 1 → 1 (address, index register): ≤16

Latency operand 1 → 1 (memory): 16

Latency operand 1 → 3 (address, base register): 6

Latency operand 1 → 3 (address, index register): 6

Latency operand 1 → 3 (memory): ≤9

Latency operand 1 → 4 (address, base register): 16

Latency operand 1 → 4 (address, index register): 16

Latency operand 1 → 4 (memory): ≤9

Latency operand 2 → 1: ≤8

Latency operand 2 → 3: 0

Latency operand 2 → 4: 0

Latency operand 3 → 1: ≤9

Latency operand 3 → 3: 2

Latency operand 3 → 4: 1


Latency operand 1 → 1 (address, base register): ≤16

Experiment 1 (with R8=0)

Experiment 2 (with R8=1)

Experiment 3 (with R8=2)

Experiment 4 (with additional nop, with R8=0)

Experiment 5 (with additional nop, with R8=1)

Experiment 6 (with additional nop, with R8=2)


Latency operand 1 → 1 (address, index register): ≤16

Experiment 1

Experiment 2 (with additional nop)


Latency operand 1 → 1 (memory): 16

Experiment 1 (with R8=0)

Experiment 2 (with R8=0, with dependency-breaking instructions)

Experiment 3 (with R8=1)

Experiment 4 (with R8=1, with dependency-breaking instructions)

Experiment 5 (with R8=2)

Experiment 6 (with R8=2, with dependency-breaking instructions)

Experiment 7 (with R8=0)

Experiment 8 (with R8=0, with dependency-breaking instructions)

Experiment 9 (with R8=1)

Experiment 10 (with R8=1, with dependency-breaking instructions)

Experiment 11 (with R8=2)

Experiment 12 (with R8=2, with dependency-breaking instructions)


Latency operand 1 → 3 (address, base register): 6

Experiment 1 (with R8=0)

Experiment 2 (with R8=1)

Experiment 3 (with R8=2)


Latency operand 1 → 3 (address, index register): 6

Experiment 1


Latency operand 1 → 3 (memory): ≤9

Experiment 1 (with R8=0)

Experiment 2 (with R8=1)

Experiment 3 (with R8=2)


Latency operand 1 → 4 (address, base register): 16

Experiment 1 (with R8=0)

Experiment 2 (with R8=0, with dependency-breaking instructions)

Experiment 3 (with R8=1)

Experiment 4 (with R8=1, with dependency-breaking instructions)

Experiment 5 (with R8=2)

Experiment 6 (with R8=2, with dependency-breaking instructions)

Experiment 7 (with R8=0)

Experiment 8 (with R8=0, with dependency-breaking instructions)

Experiment 9 (with R8=1)

Experiment 10 (with R8=1, with dependency-breaking instructions)

Experiment 11 (with R8=2)

Experiment 12 (with R8=2, with dependency-breaking instructions)

Experiment 13 (with R8=0)

Experiment 14 (with R8=0, with dependency-breaking instructions)

Experiment 15 (with R8=1)

Experiment 16 (with R8=1, with dependency-breaking instructions)

Experiment 17 (with R8=2)

Experiment 18 (with R8=2, with dependency-breaking instructions)

Experiment 19 (with R8=0)

Experiment 20 (with R8=0, with dependency-breaking instructions)

Experiment 21 (with R8=1)

Experiment 22 (with R8=1, with dependency-breaking instructions)

Experiment 23 (with R8=2)

Experiment 24 (with R8=2, with dependency-breaking instructions)

Experiment 25 (with R8=0)

Experiment 26 (with R8=0, with dependency-breaking instructions)

Experiment 27 (with R8=1)

Experiment 28 (with R8=1, with dependency-breaking instructions)

Experiment 29 (with R8=2)

Experiment 30 (with R8=2, with dependency-breaking instructions)


Latency operand 1 → 4 (address, index register): 16

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7

Experiment 8 (with dependency-breaking instructions)

Experiment 9

Experiment 10 (with dependency-breaking instructions)


Latency operand 1 → 4 (memory): ≤9

Experiment 1 (with R8=0)

Experiment 2 (with R8=1)

Experiment 3 (with R8=2)

Experiment 4 (with R8=0)

Experiment 5 (with R8=1)

Experiment 6 (with R8=2)

Experiment 7 (with R8=0)

Experiment 8 (with R8=1)

Experiment 9 (with R8=2)

Experiment 10 (with R8=0)

Experiment 11 (with R8=1)

Experiment 12 (with R8=2)

Experiment 13 (with R8=0)

Experiment 14 (with R8=1)

Experiment 15 (with R8=2)


Latency operand 2 → 1: ≤8

Experiment 1


Latency operand 2 → 3: 0

Experiment 1


Latency operand 2 → 4: 0

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5


Latency operand 3 → 1: ≤9

Experiment 1 (with R8=0)

Experiment 2 (with R8=1)

Experiment 3 (with R8=2)


Latency operand 3 → 3: 2

Experiment 1 (with R8=0)

Experiment 2 (with R8=1)

Experiment 3 (with R8=2)

Experiment 4 (with R8=0)

Experiment 5 (with R8=0, with dependency-breaking instructions)

Experiment 6 (with R8=1)

Experiment 7 (with R8=1, with dependency-breaking instructions)

Experiment 8 (with R8=2)

Experiment 9 (with R8=2, with dependency-breaking instructions)


Latency operand 3 → 4: 1

Experiment 1 (with R8=0)

Experiment 2 (with R8=1)

Experiment 3 (with R8=2)

Experiment 4 (with R8=0)

Experiment 5 (with R8=1)

Experiment 6 (with R8=2)

Experiment 7 (with R8=0)

Experiment 8 (with R8=1)

Experiment 9 (with R8=2)

Experiment 10 (with R8=0)

Experiment 11 (with R8=1)

Experiment 12 (with R8=2)

Experiment 13 (with R8=0)

Experiment 14 (with R8=1)

Experiment 15 (with R8=2)