VUCOMISS (XMM, M32)

Operands

• Operand 1 (r): Register (XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15)
• Operand 2 (r): Memory
• Operand 3 (w, suppressed): Flags (AF: w, CF: w, OF: w, PF: w, SF: w, ZF: w)

Available performance data

• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• Ivy Bridge
• Sandy Bridge
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤3
  • Latency operand 2 → 3 (address, base register): 8
  • Latency operand 2 → 3 (address, index register): 8
  • Latency operand 2 → 3 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23A

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤9
  • Latency operand 2 → 3 (address, base register): 10
  • Latency operand 2 → 3 (address, index register): 10
  • Latency operand 2 → 3 (memory): ≤12
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
  • Microcode Sequencer (MS): 0

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤3
  • Latency operand 2 → 3 (address, base register): 8
  • Latency operand 2 → 3 (address, index register): 8
  • Latency operand 2 → 3 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤3
  • Latency operand 2 → 3 (address, base register): 8
  • Latency operand 2 → 3 (address, index register): 8
  • Latency operand 2 → 3 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤3
  • Latency operand 2 → 3 (address, base register): 8
  • Latency operand 2 → 3 (address, index register): 8
  • Latency operand 2 → 3 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23
• Documentation
• Throughput: 1.0

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤3
  • Latency operand 2 → 3 (address, base register): 8
  • Latency operand 2 → 3 (address, index register): 8
  • Latency operand 2 → 3 (memory): ≤7
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤3
  • Latency operand 2 → 3 (address, base register): 8
  • Latency operand 2 → 3 (address, index register): 8
  • Latency operand 2 → 3 (memory): ≤7
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤3
  • Latency operand 2 → 3 (address, base register): 8
  • Latency operand 2 → 3 (address, index register): 8
  • Latency operand 2 → 3 (memory): ≤7
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p0+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p0+1*p23

Coffee Lake

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤3
  • Latency operand 2 → 3 (address, base register): 8
  • Latency operand 2 → 3 (address, index register): 8
  • Latency operand 2 → 3 (memory): ≤7
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23

Kaby Lake

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤3
  • Latency operand 2 → 3 (address, base register): 8
  • Latency operand 2 → 3 (address, index register): 8
  • Latency operand 2 → 3 (memory): ≤7
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23

Skylake

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤3
  • Latency operand 2 → 3 (address, base register): 8
  • Latency operand 2 → 3 (address, index register): 8
  • Latency operand 2 → 3 (memory): ≤7
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p0+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p0+1*p23

Broadwell

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤3
  • Latency operand 2 → 3 (address, base register): 9
  • Latency operand 2 → 3 (address, index register): 9
  • Latency operand 2 → 3 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p1+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p1+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p1+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p1+1*p23

Haswell

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤3
  • Latency operand 2 → 3 (address, base register): 9
  • Latency operand 2 → 3 (address, index register): 9
  • Latency operand 2 → 3 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p1+1*p23
• IACA 2.1
• Latency: 9
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p0+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p1+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p1+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p1+1*p23

Ivy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤2
  • Latency operand 2 → 3 (address, base register): 8
  • Latency operand 2 → 3 (address, index register): 8
  • Latency operand 2 → 3 (memory): ≤7
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 2 (if an indexed addressing mode is used: 3)
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p1+1*p23
• IACA 2.1
• Latency: 8
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p0+1*p1+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p0+1*p1+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 3
• Port usage: 1*p0+1*p1+1*p23

Sandy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤2
  • Latency operand 2 → 3 (address, base register): 8
  • Latency operand 2 → 3 (address, index register): 8
  • Latency operand 2 → 3 (memory): ≤7
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 3
  • Retire slots: 2 (if an indexed addressing mode is used: 3)
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p0+1*p1+1*p23
• IACA 2.1
• Latency: 8
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p0+1*p1+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p0+1*p1+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 3
• Port usage: 1*p0+1*p1+1*p23

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤6
  • Latency operand 2 → 3 (address, base register): 10
  • Latency operand 2 → 3 (address, index register): 10
  • Latency operand 2 → 3 (memory): ≤12
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
• Port usage: 1*FP23+1*FP45

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤7
  • Latency operand 2 → 3 (address, base register): 10
  • Latency operand 2 → 3 (address, index register): 10
  • Latency operand 2 → 3 (memory): ≤11
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
• Port usage: 1*FP23+1*FP45

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤7
  • Latency operand 2 → 3 (address, base register): 10
  • Latency operand 2 → 3 (address, index register): 10
  • Latency operand 2 → 3 (memory): ≤13
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2

AMD Zen+

• Measurements
• Latencies
  • Latency operand 1 → 3: ≤7
  • Latency operand 2 → 3 (address, base register): 10
  • Latency operand 2 → 3 (address, index register): 10
  • Latency operand 2 → 3 (memory): ≤12
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2