VUCOMISS (XMM, M32)

With unroll_count=500 and no inner loop

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_RETIRED.ALL: 1.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 1.03
- UOPS_RETIRED.ALL: 1.2
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_RETIRED.ALL: 1.02
- UOPS_MS: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	c4 c1 78 2e 46 04    	vucomiss xmm0,DWORD PTR [r14+0x4]
   b:	c4 c1 78 2e 46 08    	vucomiss xmm0,DWORD PTR [r14+0x8]
  11:	c4 c1 78 2e 46 0c    	vucomiss xmm0,DWORD PTR [r14+0xc]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
MOV [R14+4], RAX;
MOV [R14+12], RAX

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 4.32
- UOPS_RETIRED.ALL: 4.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	c4 c1 78 2e 46 04    	vucomiss xmm0,DWORD PTR [r14+0x4]
   b:	c4 c1 78 2e 46 08    	vucomiss xmm0,DWORD PTR [r14+0x8]
  11:	c4 c1 78 2e 46 0c    	vucomiss xmm0,DWORD PTR [r14+0xc]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
MOV [R14+4], RAX;
MOV [R14+12], RAX

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 4.1
- UOPS_RETIRED.ALL: 5.0
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	c4 c1 78 2e 46 04    	vucomiss xmm0,DWORD PTR [r14+0x4]
   b:	c4 c1 78 2e 46 08    	vucomiss xmm0,DWORD PTR [r14+0x8]
  11:	c4 c1 78 2e 46 0c    	vucomiss xmm0,DWORD PTR [r14+0xc]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
MOV [R14+4], RAX;
MOV [R14+12], RAX

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 4.1
- UOPS_RETIRED.ALL: 4.1
- UOPS_MS: 0.0

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	c4 c1 78 2e 46 04    	vucomiss xmm0,DWORD PTR [r14+0x4]
   b:	c4 c1 78 2e 46 08    	vucomiss xmm0,DWORD PTR [r14+0x8]
  11:	c4 c1 78 2e 46 0c    	vucomiss xmm0,DWORD PTR [r14+0xc]
  17:	c4 c1 78 2e 46 10    	vucomiss xmm0,DWORD PTR [r14+0x10]
  1d:	c4 c1 78 2e 46 14    	vucomiss xmm0,DWORD PTR [r14+0x14]
  23:	c4 c1 78 2e 46 18    	vucomiss xmm0,DWORD PTR [r14+0x18]
  29:	c4 c1 78 2e 46 1c    	vucomiss xmm0,DWORD PTR [r14+0x1c]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
MOV [R14+4], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 8.64
- UOPS_RETIRED.ALL: 8.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	c4 c1 78 2e 46 04    	vucomiss xmm0,DWORD PTR [r14+0x4]
   b:	c4 c1 78 2e 46 08    	vucomiss xmm0,DWORD PTR [r14+0x8]
  11:	c4 c1 78 2e 46 0c    	vucomiss xmm0,DWORD PTR [r14+0xc]
  17:	c4 c1 78 2e 46 10    	vucomiss xmm0,DWORD PTR [r14+0x10]
  1d:	c4 c1 78 2e 46 14    	vucomiss xmm0,DWORD PTR [r14+0x14]
  23:	c4 c1 78 2e 46 18    	vucomiss xmm0,DWORD PTR [r14+0x18]
  29:	c4 c1 78 2e 46 1c    	vucomiss xmm0,DWORD PTR [r14+0x1c]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
MOV [R14+4], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.03
- Reference cycles: 8.21
- UOPS_RETIRED.ALL: 10.0
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	c4 c1 78 2e 46 04    	vucomiss xmm0,DWORD PTR [r14+0x4]
   b:	c4 c1 78 2e 46 08    	vucomiss xmm0,DWORD PTR [r14+0x8]
  11:	c4 c1 78 2e 46 0c    	vucomiss xmm0,DWORD PTR [r14+0xc]
  17:	c4 c1 78 2e 46 10    	vucomiss xmm0,DWORD PTR [r14+0x10]
  1d:	c4 c1 78 2e 46 14    	vucomiss xmm0,DWORD PTR [r14+0x14]
  23:	c4 c1 78 2e 46 18    	vucomiss xmm0,DWORD PTR [r14+0x18]
  29:	c4 c1 78 2e 46 1c    	vucomiss xmm0,DWORD PTR [r14+0x1c]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
MOV [R14+4], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.03
- Reference cycles: 8.18
- UOPS_RETIRED.ALL: 8.2
- UOPS_MS: 0.0

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	c4 c1 78 2e 46 04    	vucomiss xmm0,DWORD PTR [r14+0x4]
   b:	c4 c1 78 2e 46 08    	vucomiss xmm0,DWORD PTR [r14+0x8]
  11:	c4 c1 78 2e 46 0c    	vucomiss xmm0,DWORD PTR [r14+0xc]
  17:	c4 c1 78 2e 46 10    	vucomiss xmm0,DWORD PTR [r14+0x10]
  1d:	c4 c1 78 2e 46 14    	vucomiss xmm0,DWORD PTR [r14+0x14]
  23:	c4 c1 78 2e 46 18    	vucomiss xmm0,DWORD PTR [r14+0x18]
  29:	c4 c1 78 2e 46 1c    	vucomiss xmm0,DWORD PTR [r14+0x1c]
  2f:	c4 c1 78 2e 46 20    	vucomiss xmm0,DWORD PTR [r14+0x20]
  35:	c4 c1 78 2e 46 24    	vucomiss xmm0,DWORD PTR [r14+0x24]
  3b:	c4 c1 78 2e 46 28    	vucomiss xmm0,DWORD PTR [r14+0x28]
  41:	c4 c1 78 2e 46 2c    	vucomiss xmm0,DWORD PTR [r14+0x2c]
  47:	c4 c1 78 2e 46 30    	vucomiss xmm0,DWORD PTR [r14+0x30]
  4d:	c4 c1 78 2e 46 34    	vucomiss xmm0,DWORD PTR [r14+0x34]
  53:	c4 c1 78 2e 46 38    	vucomiss xmm0,DWORD PTR [r14+0x38]
  59:	c4 c1 78 2e 46 3c    	vucomiss xmm0,DWORD PTR [r14+0x3c]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
MOV [R14+4], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX;
MOV [R14+32], RAX;
MOV [R14+36], RAX;
MOV [R14+40], RAX;
MOV [R14+44], RAX;
MOV [R14+48], RAX;
MOV [R14+52], RAX;
MOV [R14+56], RAX;
MOV [R14+60], RAX

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 16.32
- UOPS_RETIRED.ALL: 16.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	c4 c1 78 2e 46 04    	vucomiss xmm0,DWORD PTR [r14+0x4]
   b:	c4 c1 78 2e 46 08    	vucomiss xmm0,DWORD PTR [r14+0x8]
  11:	c4 c1 78 2e 46 0c    	vucomiss xmm0,DWORD PTR [r14+0xc]
  17:	c4 c1 78 2e 46 10    	vucomiss xmm0,DWORD PTR [r14+0x10]
  1d:	c4 c1 78 2e 46 14    	vucomiss xmm0,DWORD PTR [r14+0x14]
  23:	c4 c1 78 2e 46 18    	vucomiss xmm0,DWORD PTR [r14+0x18]
  29:	c4 c1 78 2e 46 1c    	vucomiss xmm0,DWORD PTR [r14+0x1c]
  2f:	c4 c1 78 2e 46 20    	vucomiss xmm0,DWORD PTR [r14+0x20]
  35:	c4 c1 78 2e 46 24    	vucomiss xmm0,DWORD PTR [r14+0x24]
  3b:	c4 c1 78 2e 46 28    	vucomiss xmm0,DWORD PTR [r14+0x28]
  41:	c4 c1 78 2e 46 2c    	vucomiss xmm0,DWORD PTR [r14+0x2c]
  47:	c4 c1 78 2e 46 30    	vucomiss xmm0,DWORD PTR [r14+0x30]
  4d:	c4 c1 78 2e 46 34    	vucomiss xmm0,DWORD PTR [r14+0x34]
  53:	c4 c1 78 2e 46 38    	vucomiss xmm0,DWORD PTR [r14+0x38]
  59:	c4 c1 78 2e 46 3c    	vucomiss xmm0,DWORD PTR [r14+0x3c]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
MOV [R14+4], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX;
MOV [R14+32], RAX;
MOV [R14+36], RAX;
MOV [R14+40], RAX;
MOV [R14+44], RAX;
MOV [R14+48], RAX;
MOV [R14+52], RAX;
MOV [R14+56], RAX;
MOV [R14+60], RAX

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.03
- Reference cycles: 16.38
- UOPS_RETIRED.ALL: 18.0
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	c4 c1 78 2e 46 04    	vucomiss xmm0,DWORD PTR [r14+0x4]
   b:	c4 c1 78 2e 46 08    	vucomiss xmm0,DWORD PTR [r14+0x8]
  11:	c4 c1 78 2e 46 0c    	vucomiss xmm0,DWORD PTR [r14+0xc]
  17:	c4 c1 78 2e 46 10    	vucomiss xmm0,DWORD PTR [r14+0x10]
  1d:	c4 c1 78 2e 46 14    	vucomiss xmm0,DWORD PTR [r14+0x14]
  23:	c4 c1 78 2e 46 18    	vucomiss xmm0,DWORD PTR [r14+0x18]
  29:	c4 c1 78 2e 46 1c    	vucomiss xmm0,DWORD PTR [r14+0x1c]
  2f:	c4 c1 78 2e 46 20    	vucomiss xmm0,DWORD PTR [r14+0x20]
  35:	c4 c1 78 2e 46 24    	vucomiss xmm0,DWORD PTR [r14+0x24]
  3b:	c4 c1 78 2e 46 28    	vucomiss xmm0,DWORD PTR [r14+0x28]
  41:	c4 c1 78 2e 46 2c    	vucomiss xmm0,DWORD PTR [r14+0x2c]
  47:	c4 c1 78 2e 46 30    	vucomiss xmm0,DWORD PTR [r14+0x30]
  4d:	c4 c1 78 2e 46 34    	vucomiss xmm0,DWORD PTR [r14+0x34]
  53:	c4 c1 78 2e 46 38    	vucomiss xmm0,DWORD PTR [r14+0x38]
  59:	c4 c1 78 2e 46 3c    	vucomiss xmm0,DWORD PTR [r14+0x3c]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
MOV [R14+4], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX;
MOV [R14+32], RAX;
MOV [R14+36], RAX;
MOV [R14+40], RAX;
MOV [R14+44], RAX;
MOV [R14+48], RAX;
MOV [R14+52], RAX;
MOV [R14+56], RAX;
MOV [R14+60], RAX

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.03
- Reference cycles: 16.4
- UOPS_RETIRED.ALL: 16.2
- UOPS_MS: 0.0

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

Code:

   0:	c4 81 78 2e 04 2e    	vucomiss xmm0,DWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_RETIRED.ALL: 1.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=10

Code:

   0:	c4 81 78 2e 04 2e    	vucomiss xmm0,DWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.2
- Core cycles: 1.0
- Reference cycles: 1.03
- UOPS_RETIRED.ALL: 1.2
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=100

Code:

   0:	c4 81 78 2e 04 2e    	vucomiss xmm0,DWORD PTR [r14+r13*1]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 1.02
- Core cycles: 1.0
- Reference cycles: 1.02
- UOPS_RETIRED.ALL: 1.02
- UOPS_MS: 0.0

With 4 independent instructions

With unroll_count=200 and no inner loop

Code:

   0:	c4 81 78 2e 04 2e    	vucomiss xmm0,DWORD PTR [r14+r13*1]
   6:	c4 81 78 2e 44 2e 04 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x4]
   d:	c4 81 78 2e 44 2e 08 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x8]
  14:	c4 81 78 2e 44 2e 0c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0xc]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+12], RAX

Show nanoBench command
Results:
- Instructions retired: 4.0
- Core cycles: 4.0
- Reference cycles: 4.0
- UOPS_RETIRED.ALL: 4.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=2

Code:

   0:	c4 81 78 2e 04 2e    	vucomiss xmm0,DWORD PTR [r14+r13*1]
   6:	c4 81 78 2e 44 2e 04 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x4]
   d:	c4 81 78 2e 44 2e 08 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x8]
  14:	c4 81 78 2e 44 2e 0c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0xc]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+12], RAX

Show nanoBench command
Results:
- Instructions retired: 5.0
- Core cycles: 4.01
- Reference cycles: 4.1
- UOPS_RETIRED.ALL: 5.0
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=20

Code:

   0:	c4 81 78 2e 04 2e    	vucomiss xmm0,DWORD PTR [r14+r13*1]
   6:	c4 81 78 2e 44 2e 04 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x4]
   d:	c4 81 78 2e 44 2e 08 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x8]
  14:	c4 81 78 2e 44 2e 0c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0xc]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+12], RAX

Show nanoBench command
Results:
- Instructions retired: 4.1
- Core cycles: 4.01
- Reference cycles: 4.1
- UOPS_RETIRED.ALL: 4.1
- UOPS_MS: 0.0

With 8 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 81 78 2e 04 2e    	vucomiss xmm0,DWORD PTR [r14+r13*1]
   6:	c4 81 78 2e 44 2e 04 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x4]
   d:	c4 81 78 2e 44 2e 08 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x8]
  14:	c4 81 78 2e 44 2e 0c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0xc]
  1b:	c4 81 78 2e 44 2e 10 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x10]
  22:	c4 81 78 2e 44 2e 14 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x14]
  29:	c4 81 78 2e 44 2e 18 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x18]
  30:	c4 81 78 2e 44 2e 1c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x1c]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 8.32
- UOPS_RETIRED.ALL: 8.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 81 78 2e 04 2e    	vucomiss xmm0,DWORD PTR [r14+r13*1]
   6:	c4 81 78 2e 44 2e 04 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x4]
   d:	c4 81 78 2e 44 2e 08 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x8]
  14:	c4 81 78 2e 44 2e 0c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0xc]
  1b:	c4 81 78 2e 44 2e 10 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x10]
  22:	c4 81 78 2e 44 2e 14 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x14]
  29:	c4 81 78 2e 44 2e 18 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x18]
  30:	c4 81 78 2e 44 2e 1c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x1c]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 8.03
- Reference cycles: 8.19
- UOPS_RETIRED.ALL: 10.0
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 81 78 2e 04 2e    	vucomiss xmm0,DWORD PTR [r14+r13*1]
   6:	c4 81 78 2e 44 2e 04 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x4]
   d:	c4 81 78 2e 44 2e 08 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x8]
  14:	c4 81 78 2e 44 2e 0c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0xc]
  1b:	c4 81 78 2e 44 2e 10 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x10]
  22:	c4 81 78 2e 44 2e 14 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x14]
  29:	c4 81 78 2e 44 2e 18 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x18]
  30:	c4 81 78 2e 44 2e 1c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x1c]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX

Show nanoBench command
Results:
- Instructions retired: 8.2
- Core cycles: 8.03
- Reference cycles: 8.22
- UOPS_RETIRED.ALL: 8.2
- UOPS_MS: 0.0

With 16 independent instructions

With unroll_count=100 and no inner loop

Code:

   0:	c4 81 78 2e 04 2e    	vucomiss xmm0,DWORD PTR [r14+r13*1]
   6:	c4 81 78 2e 44 2e 04 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x4]
   d:	c4 81 78 2e 44 2e 08 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x8]
  14:	c4 81 78 2e 44 2e 0c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0xc]
  1b:	c4 81 78 2e 44 2e 10 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x10]
  22:	c4 81 78 2e 44 2e 14 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x14]
  29:	c4 81 78 2e 44 2e 18 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x18]
  30:	c4 81 78 2e 44 2e 1c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x1c]
  37:	c4 81 78 2e 44 2e 20 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x20]
  3e:	c4 81 78 2e 44 2e 24 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x24]
  45:	c4 81 78 2e 44 2e 28 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x28]
  4c:	c4 81 78 2e 44 2e 2c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x2c]
  53:	c4 81 78 2e 44 2e 30 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x30]
  5a:	c4 81 78 2e 44 2e 34 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x34]
  61:	c4 81 78 2e 44 2e 38 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x38]
  68:	c4 81 78 2e 44 2e 3c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x3c]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX;
MOV [R14+32], RAX;
MOV [R14+36], RAX;
MOV [R14+40], RAX;
MOV [R14+44], RAX;
MOV [R14+48], RAX;
MOV [R14+52], RAX;
MOV [R14+56], RAX;
MOV [R14+60], RAX

Show nanoBench command
Results:
- Instructions retired: 16.0
- Core cycles: 16.0
- Reference cycles: 16.0
- UOPS_RETIRED.ALL: 16.0
- UOPS_MS: 0.0

With loop_count=1000 and unroll_count=1

Code:

   0:	c4 81 78 2e 04 2e    	vucomiss xmm0,DWORD PTR [r14+r13*1]
   6:	c4 81 78 2e 44 2e 04 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x4]
   d:	c4 81 78 2e 44 2e 08 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x8]
  14:	c4 81 78 2e 44 2e 0c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0xc]
  1b:	c4 81 78 2e 44 2e 10 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x10]
  22:	c4 81 78 2e 44 2e 14 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x14]
  29:	c4 81 78 2e 44 2e 18 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x18]
  30:	c4 81 78 2e 44 2e 1c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x1c]
  37:	c4 81 78 2e 44 2e 20 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x20]
  3e:	c4 81 78 2e 44 2e 24 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x24]
  45:	c4 81 78 2e 44 2e 28 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x28]
  4c:	c4 81 78 2e 44 2e 2c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x2c]
  53:	c4 81 78 2e 44 2e 30 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x30]
  5a:	c4 81 78 2e 44 2e 34 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x34]
  61:	c4 81 78 2e 44 2e 38 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x38]
  68:	c4 81 78 2e 44 2e 3c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x3c]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX;
MOV [R14+32], RAX;
MOV [R14+36], RAX;
MOV [R14+40], RAX;
MOV [R14+44], RAX;
MOV [R14+48], RAX;
MOV [R14+52], RAX;
MOV [R14+56], RAX;
MOV [R14+60], RAX

Show nanoBench command
Results:
- Instructions retired: 18.0
- Core cycles: 16.03
- Reference cycles: 16.45
- UOPS_RETIRED.ALL: 18.0
- UOPS_MS: 0.0

With loop_count=100 and unroll_count=10

Code:

   0:	c4 81 78 2e 04 2e    	vucomiss xmm0,DWORD PTR [r14+r13*1]
   6:	c4 81 78 2e 44 2e 04 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x4]
   d:	c4 81 78 2e 44 2e 08 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x8]
  14:	c4 81 78 2e 44 2e 0c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0xc]
  1b:	c4 81 78 2e 44 2e 10 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x10]
  22:	c4 81 78 2e 44 2e 14 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x14]
  29:	c4 81 78 2e 44 2e 18 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x18]
  30:	c4 81 78 2e 44 2e 1c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x1c]
  37:	c4 81 78 2e 44 2e 20 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x20]
  3e:	c4 81 78 2e 44 2e 24 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x24]
  45:	c4 81 78 2e 44 2e 28 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x28]
  4c:	c4 81 78 2e 44 2e 2c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x2c]
  53:	c4 81 78 2e 44 2e 30 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x30]
  5a:	c4 81 78 2e 44 2e 34 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x34]
  61:	c4 81 78 2e 44 2e 38 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x38]
  68:	c4 81 78 2e 44 2e 3c 	vucomiss xmm0,DWORD PTR [r14+r13*1+0x3c]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
XOR R13, R13;
MOV [R14+4], RAX;
MOV [R14+12], RAX;
MOV [R14+16], RAX;
MOV [R14+20], RAX;
MOV [R14+24], RAX;
MOV [R14+28], RAX;
MOV [R14+32], RAX;
MOV [R14+36], RAX;
MOV [R14+40], RAX;
MOV [R14+44], RAX;
MOV [R14+48], RAX;
MOV [R14+52], RAX;
MOV [R14+56], RAX;
MOV [R14+60], RAX

Show nanoBench command
Results:
- Instructions retired: 16.2
- Core cycles: 16.03
- Reference cycles: 16.42
- UOPS_RETIRED.ALL: 16.2
- UOPS_MS: 0.0

VUCOMISS (XMM, M32) - Throughput and Uops

With a non-indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With an indexed addressing mode

With 1 independent instruction

With unroll_count=500 and no inner loop

With loop_count=1000 and unroll_count=10

With loop_count=100 and unroll_count=100

With 4 independent instructions

With unroll_count=200 and no inner loop

With loop_count=1000 and unroll_count=2

With loop_count=100 and unroll_count=20

With 8 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10

With 16 independent instructions

With unroll_count=100 and no inner loop

With loop_count=1000 and unroll_count=1

With loop_count=100 and unroll_count=10