VUCOMISS (XMM, M32)

Experiment 1

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVS R12, R15; VCVTSI2SS XMM0, XMM1, R12D
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 48 e7          	cmovs  r12,r15
   9:	c4 c1 72 2a c4       	vcvtsi2ss xmm0,xmm1,r12d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 9.01
- Reference cycles: 6.72
- UOPS_EXECUTED.THREAD: 5.0

Experiment 2

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVS R12, R15; VCVTSI2SS XMM0, XMM1, R12
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 48 e7          	cmovs  r12,r15
   9:	c4 c1 f2 2a c4       	vcvtsi2ss xmm0,xmm1,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 10.01
- Reference cycles: 7.36
- UOPS_EXECUTED.THREAD: 5.95

Experiment 3

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVS R12, R15; VMOVD XMM0, R12D
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 48 e7          	cmovs  r12,r15
   9:	c4 c1 79 6e c4       	vmovd  xmm0,r12d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 5.01
- Reference cycles: 3.84
- UOPS_EXECUTED.THREAD: 3.98

Experiment 4

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVS R12, R15; VMOVQ XMM0, R12
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 48 e7          	cmovs  r12,r15
   9:	c4 c1 f9 6e c4       	vmovq  xmm0,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 5.01
- Reference cycles: 3.84
- UOPS_EXECUTED.THREAD: 3.99

Experiment 5

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVS R12, R15; VPINSRB XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 48 e7          	cmovs  r12,r15
   9:	c4 c3 71 20 c4 02    	vpinsrb xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.02
- Reference cycles: 4.16
- UOPS_EXECUTED.THREAD: 4.98

Experiment 6

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVS R12, R15; VPINSRD XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 48 e7          	cmovs  r12,r15
   9:	c4 c3 71 22 c4 02    	vpinsrd xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.02
- Reference cycles: 4.8
- UOPS_EXECUTED.THREAD: 5.0

Experiment 7

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVS R12, R15; VPINSRQ XMM0, XMM1, R12, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 48 e7          	cmovs  r12,r15
   9:	c4 c3 f1 22 c4 02    	vpinsrq xmm0,xmm1,r12,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.03
- Reference cycles: 4.48
- UOPS_EXECUTED.THREAD: 5.01

Experiment 8

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVS R12, R15; VPINSRW XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 48 e7          	cmovs  r12,r15
   9:	c4 c1 71 c4 c4 02    	vpinsrw xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.02
- Reference cycles: 4.48
- UOPS_EXECUTED.THREAD: 5.0

Experiment 9

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVP R12, R15; VCVTSI2SS XMM0, XMM1, R12D
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 4a e7          	cmovp  r12,r15
   9:	c4 c1 72 2a c4       	vcvtsi2ss xmm0,xmm1,r12d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 9.0
- Reference cycles: 6.72
- UOPS_EXECUTED.THREAD: 5.01

Experiment 10

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVP R12, R15; VCVTSI2SS XMM0, XMM1, R12
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 4a e7          	cmovp  r12,r15
   9:	c4 c1 f2 2a c4       	vcvtsi2ss xmm0,xmm1,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 10.0
- Reference cycles: 7.36
- UOPS_EXECUTED.THREAD: 5.99

Experiment 11

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVP R12, R15; VMOVD XMM0, R12D
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 4a e7          	cmovp  r12,r15
   9:	c4 c1 79 6e c4       	vmovd  xmm0,r12d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 5.0
- Reference cycles: 3.52
- UOPS_EXECUTED.THREAD: 4.01

Experiment 12

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVP R12, R15; VMOVQ XMM0, R12
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 4a e7          	cmovp  r12,r15
   9:	c4 c1 f9 6e c4       	vmovq  xmm0,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 5.01
- Reference cycles: 3.84
- UOPS_EXECUTED.THREAD: 3.98

Experiment 13

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVP R12, R15; VPINSRB XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 4a e7          	cmovp  r12,r15
   9:	c4 c3 71 20 c4 02    	vpinsrb xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.03
- Reference cycles: 4.32
- UOPS_EXECUTED.THREAD: 4.98

Experiment 14

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVP R12, R15; VPINSRD XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 4a e7          	cmovp  r12,r15
   9:	c4 c3 71 22 c4 02    	vpinsrd xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.05
- Reference cycles: 4.8
- UOPS_EXECUTED.THREAD: 5.04

Experiment 15

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVP R12, R15; VPINSRQ XMM0, XMM1, R12, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 4a e7          	cmovp  r12,r15
   9:	c4 c3 f1 22 c4 02    	vpinsrq xmm0,xmm1,r12,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.03
- Reference cycles: 4.48
- UOPS_EXECUTED.THREAD: 4.97

Experiment 16

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVP R12, R15; VPINSRW XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 4a e7          	cmovp  r12,r15
   9:	c4 c1 71 c4 c4 02    	vpinsrw xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.02
- Reference cycles: 4.16
- UOPS_EXECUTED.THREAD: 4.98

Experiment 17

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVC R12, R15; VCVTSI2SS XMM0, XMM1, R12D
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 42 e7          	cmovb  r12,r15
   9:	c4 c1 72 2a c4       	vcvtsi2ss xmm0,xmm1,r12d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 9.01
- Reference cycles: 6.72
- UOPS_EXECUTED.THREAD: 5.0

Experiment 18

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVC R12, R15; VCVTSI2SS XMM0, XMM1, R12
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 42 e7          	cmovb  r12,r15
   9:	c4 c1 f2 2a c4       	vcvtsi2ss xmm0,xmm1,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 10.04
- Reference cycles: 7.68
- UOPS_EXECUTED.THREAD: 5.98

Experiment 19

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVC R12, R15; VMOVD XMM0, R12D
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 42 e7          	cmovb  r12,r15
   9:	c4 c1 79 6e c4       	vmovd  xmm0,r12d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 5.01
- Reference cycles: 3.52
- UOPS_EXECUTED.THREAD: 3.99

Experiment 20

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVC R12, R15; VMOVQ XMM0, R12
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 42 e7          	cmovb  r12,r15
   9:	c4 c1 f9 6e c4       	vmovq  xmm0,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 5.01
- Reference cycles: 4.0
- UOPS_EXECUTED.THREAD: 3.98

Experiment 21

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVC R12, R15; VPINSRB XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 42 e7          	cmovb  r12,r15
   9:	c4 c3 71 20 c4 02    	vpinsrb xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.02
- Reference cycles: 4.64
- UOPS_EXECUTED.THREAD: 4.99

Experiment 22

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVC R12, R15; VPINSRD XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 42 e7          	cmovb  r12,r15
   9:	c4 c3 71 22 c4 02    	vpinsrd xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.03
- Reference cycles: 4.32
- UOPS_EXECUTED.THREAD: 4.98

Experiment 23

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVC R12, R15; VPINSRQ XMM0, XMM1, R12, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 42 e7          	cmovb  r12,r15
   9:	c4 c3 f1 22 c4 02    	vpinsrq xmm0,xmm1,r12,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.03
- Reference cycles: 4.16
- UOPS_EXECUTED.THREAD: 5.01

Experiment 24

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVC R12, R15; VPINSRW XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 42 e7          	cmovb  r12,r15
   9:	c4 c1 71 c4 c4 02    	vpinsrw xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.04
- Reference cycles: 4.32
- UOPS_EXECUTED.THREAD: 4.99

Experiment 25

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVZ R12, R15; VCVTSI2SS XMM0, XMM1, R12D
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 44 e7          	cmove  r12,r15
   9:	c4 c1 72 2a c4       	vcvtsi2ss xmm0,xmm1,r12d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 9.01
- Reference cycles: 6.72
- UOPS_EXECUTED.THREAD: 5.0

Experiment 26

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVZ R12, R15; VCVTSI2SS XMM0, XMM1, R12
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 44 e7          	cmove  r12,r15
   9:	c4 c1 f2 2a c4       	vcvtsi2ss xmm0,xmm1,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 9.99
- Reference cycles: 7.52
- UOPS_EXECUTED.THREAD: 5.96

Experiment 27

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVZ R12, R15; VMOVD XMM0, R12D
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 44 e7          	cmove  r12,r15
   9:	c4 c1 79 6e c4       	vmovd  xmm0,r12d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 5.04
- Reference cycles: 3.84
- UOPS_EXECUTED.THREAD: 4.0

Experiment 28

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVZ R12, R15; VMOVQ XMM0, R12
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 44 e7          	cmove  r12,r15
   9:	c4 c1 f9 6e c4       	vmovq  xmm0,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 5.01
- Reference cycles: 3.84
- UOPS_EXECUTED.THREAD: 3.98

Experiment 29

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVZ R12, R15; VPINSRB XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 44 e7          	cmove  r12,r15
   9:	c4 c3 71 20 c4 02    	vpinsrb xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.02
- Reference cycles: 4.16
- UOPS_EXECUTED.THREAD: 4.98

Experiment 30

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVZ R12, R15; VPINSRD XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 44 e7          	cmove  r12,r15
   9:	c4 c3 71 22 c4 02    	vpinsrd xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.03
- Reference cycles: 4.16
- UOPS_EXECUTED.THREAD: 5.0

Experiment 31

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVZ R12, R15; VPINSRQ XMM0, XMM1, R12, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 44 e7          	cmove  r12,r15
   9:	c4 c3 f1 22 c4 02    	vpinsrq xmm0,xmm1,r12,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.03
- Reference cycles: 4.96
- UOPS_EXECUTED.THREAD: 4.98

Experiment 32

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVZ R12, R15; VPINSRW XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 44 e7          	cmove  r12,r15
   9:	c4 c1 71 c4 c4 02    	vpinsrw xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.03
- Reference cycles: 4.0
- UOPS_EXECUTED.THREAD: 4.99

Experiment 33

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVO R12, R15; VCVTSI2SS XMM0, XMM1, R12D
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 40 e7          	cmovo  r12,r15
   9:	c4 c1 72 2a c4       	vcvtsi2ss xmm0,xmm1,r12d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 9.0
- Reference cycles: 6.72
- UOPS_EXECUTED.THREAD: 4.98

Experiment 34

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVO R12, R15; VCVTSI2SS XMM0, XMM1, R12
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 40 e7          	cmovo  r12,r15
   9:	c4 c1 f2 2a c4       	vcvtsi2ss xmm0,xmm1,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 9.99
- Reference cycles: 7.52
- UOPS_EXECUTED.THREAD: 5.99

Experiment 35

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVO R12, R15; VMOVD XMM0, R12D
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 40 e7          	cmovo  r12,r15
   9:	c4 c1 79 6e c4       	vmovd  xmm0,r12d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 5.0
- Reference cycles: 3.52
- UOPS_EXECUTED.THREAD: 3.99

Experiment 36

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVO R12, R15; VMOVQ XMM0, R12
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 40 e7          	cmovo  r12,r15
   9:	c4 c1 f9 6e c4       	vmovq  xmm0,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 5.0
- Reference cycles: 3.84
- UOPS_EXECUTED.THREAD: 3.98

Experiment 37

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVO R12, R15; VPINSRB XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 40 e7          	cmovo  r12,r15
   9:	c4 c3 71 20 c4 02    	vpinsrb xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.03
- Reference cycles: 4.32
- UOPS_EXECUTED.THREAD: 4.98

Experiment 38

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVO R12, R15; VPINSRD XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 40 e7          	cmovo  r12,r15
   9:	c4 c3 71 22 c4 02    	vpinsrd xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.06
- Reference cycles: 4.64
- UOPS_EXECUTED.THREAD: 5.01

Experiment 39

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVO R12, R15; VPINSRQ XMM0, XMM1, R12, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 40 e7          	cmovo  r12,r15
   9:	c4 c3 f1 22 c4 02    	vpinsrq xmm0,xmm1,r12,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.04
- Reference cycles: 3.84
- UOPS_EXECUTED.THREAD: 4.99

Experiment 40

Instruction: VUCOMISS XMM0, dword ptr [R14]
Chain instructions: CMOVO R12, R15; VPINSRW XMM0, XMM1, R12D, 2
Chain latency: ≥2

Code:

   0:	c4 c1 78 2e 06       	vucomiss xmm0,DWORD PTR [r14]
   5:	4d 0f 40 e7          	cmovo  r12,r15
   9:	c4 c1 71 c4 c4 02    	vpinsrw xmm0,xmm1,r12d,0x2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.03
- Reference cycles: 4.48
- UOPS_EXECUTED.THREAD: 5.0

VUCOMISS (XMM, M32) - Latency

Operands

Latency operand 1 → 3: ≤3

Latency operand 2 → 3 (address, base register): 8

Latency operand 2 → 3 (address, index register): 8

Latency operand 2 → 3 (memory): ≤8

Latency operand 1 → 3: ≤3

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6

Experiment 7

Experiment 8

Experiment 9

Experiment 10

Experiment 11

Experiment 12

Experiment 13

Experiment 14

Experiment 15

Experiment 16

Experiment 17

Experiment 18

Experiment 19

Experiment 20

Experiment 21

Experiment 22

Experiment 23

Experiment 24

Experiment 25

Experiment 26

Experiment 27

Experiment 28

Experiment 29

Experiment 30

Experiment 31

Experiment 32

Experiment 33

Experiment 34

Experiment 35

Experiment 36

Experiment 37

Experiment 38

Experiment 39

Experiment 40

Latency operand 2 → 3 (address, base register): 8

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Latency operand 2 → 3 (address, index register): 8

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Latency operand 2 → 3 (memory): ≤8

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5