VPSRLW (YMM, YMM, XMM)
Summary:
"Shift Packed Data Right Logical"
Reference:
https://www.felixcloutier.com/x86/psrlw:psrld:psrlq
Extension:
AVX2
Category:
AVX2
ISA-Set:
AVX2
CPL:
3
iform:
VPSRLW_YMMqq_YMMqq_XMMq
iclass:
VPSRLW
ASM:
VPSRLW
Operands
Operand 1 (w): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)
Operand 2 (r): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)
Operand 3 (r): Register (XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15)
Available performance data
Arrow Lake-P
Arrow Lake-E
Meteor Lake-P
Meteor Lake-E
Emerald Rapids
Alder Lake-P
Alder Lake-E
Rocket Lake
Tiger Lake
Ice Lake
Cascade Lake
Cannon Lake
Skylake-X
Coffee Lake
Kaby Lake
Skylake
Broadwell
Haswell
AMD Zen 5
AMD Zen 4
AMD Zen 3
AMD Zen 2
AMD Zen+
Arrow Lake-P
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Measured (loop):
0.50
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (6 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
2*UNKNOWN
Arrow Lake-E
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
1
Throughput
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 2
Microcode Sequencer (MS): 0
Meteor Lake-P
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p01+1*p5
Meteor Lake-E
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
1
Throughput
Measured (loop):
0.67
Measured (unrolled):
0.67
Number of μops
Executed: 2
Microcode Sequencer (MS): 0
Emerald Rapids
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p01+1*p5
Alder Lake-P
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p01+1*p5
Alder Lake-E
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
1
Throughput
Measured (loop):
0.67
Measured (unrolled):
0.67
Number of μops
Executed: 2
Microcode Sequencer (MS): 0
Rocket Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p01+1*p5
Tiger Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p01+1*p5
Ice Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p01+1*p5
Documentation
Throughput: 1.0
Cascade Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p01+1*p5
Cannon Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p01+1*p5
Skylake-X
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p01+1*p5
IACA 2.3
Throughput
Computed from the port usage: 1.00
IACA:
1.00
Number of μops:
2
Port usage:
1*p01+1*p5
IACA 3.0
Throughput
Computed from the port usage: 1.00
IACA:
0.97
Number of μops:
2
Port usage:
1*p01+1*p5
Coffee Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p01+1*p5
Kaby Lake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p01+1*p5
Skylake
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
Port usage:
1*p01+1*p5
IACA 2.3
Throughput
Computed from the port usage: 1.00
IACA:
1.00
Number of μops:
2
Port usage:
1*p01+1*p5
IACA 3.0
Throughput
Computed from the port usage: 1.00
IACA:
0.97
Number of μops:
2
Port usage:
1*p01+1*p5
Broadwell
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0+1*p5
IACA 2.2
Throughput
Computed from the port usage: 1.00
IACA:
1.00 (with the -no_interiteration flag: 1.00)
Number of μops:
2
Port usage:
1*p0+1*p5
IACA 2.3
Throughput
Computed from the port usage: 1.00
IACA:
1.00
Number of μops:
2
Port usage:
1*p0+1*p5
IACA 3.0
Throughput
Computed from the port usage: 1.00
IACA:
0.97
Number of μops:
2
Port usage:
1*p0+1*p5
Haswell
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
4
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 2
Retire slots: 2
Decoded (MITE): 2
Microcode Sequencer (MS): 0
Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
Port usage:
1*p0+1*p5
IACA 2.1
Latency:
4
Throughput
Computed from the port usage: 1.00
IACA:
1.00 (with the -no_interiteration flag: 1.00)
Number of μops:
2
Port usage:
1*p0+1*p5
IACA 2.2
Throughput
Computed from the port usage: 1.00
IACA:
1.00 (with the -no_interiteration flag: 1.00)
Number of μops:
2
Port usage:
1*p0+1*p5
IACA 2.3
Throughput
Computed from the port usage: 1.00
IACA:
1.00
Number of μops:
2
Port usage:
1*p0+1*p5
IACA 3.0
Throughput
Computed from the port usage: 1.00
IACA:
0.97
Number of μops:
2
Port usage:
1*p0+1*p5
AMD Zen 5
Measurements
Latencies
Latency operand 2 → 1:
2
Latency operand 3 → 1:
2
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Port usage:
1*FP01
Documentation
Latency: 2
Throughput: 0.50
Number of μops: 1
Port usage: FP0/1
AMD Zen 4
Measurements
Latencies
Latency operand 2 → 1:
2
Latency operand 3 → 1:
2
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Port usage:
1*FP01
AMD Zen 3
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
1
Throughput
Computed from the port usage: 0.50
Measured (loop):
0.50
Measured (unrolled):
0.50
Number of μops
Executed: 1
Port usage:
1*FP12
AMD Zen 2
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
1
Throughput
Computed from the port usage: 1.00
Measured (loop):
1.00
Measured (unrolled):
1.00
Number of μops
Executed: 1
Port usage:
1*FP2
AMD Zen+
Measurements
Latencies
Latency operand 2 → 1:
1
Latency operand 3 → 1:
2
Throughput
Measured (loop):
2.00
Measured (unrolled):
2.00
Number of μops
Executed: 2