VPSRLW (YMM, YMM, XMM)

Experiment 1

Instruction: VPSRLW YMM1, YMM0, XMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 fd d1 ca          	vpsrlw ymm1,ymm0,xmm2
   4:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   9:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  13:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  18:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.98
- Reference cycles: 6.0
- UOPS_EXECUTED.THREAD: 7.0

Experiment 2

Instruction: VPSRLW YMM1, YMM0, XMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c5 fd d1 ca          	vpsrlw ymm1,ymm0,xmm2
   4:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   8:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   c:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  10:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  14:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS XMM2, XMM2, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.5
- Reference cycles: 6.0
- UOPS_EXECUTED.THREAD: 7.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPSRLW YMM1, YMM0, XMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c5 fd d1 ca          	vpsrlw ymm1,ymm0,xmm2
   4:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   9:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  13:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  18:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS XMM2, XMM2, XMM2;
VPSRLW YMM0, YMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.99
- Reference cycles: 6.5
- UOPS_EXECUTED.THREAD: 7.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPSRLW YMM1, YMM0, XMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c5 fd d1 ca          	vpsrlw ymm1,ymm0,xmm2
   4:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   8:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   c:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  10:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  14:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS XMM2, XMM2, XMM2;
VPSRLW YMM0, YMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 6.64
- Reference cycles: 6.0
- UOPS_EXECUTED.THREAD: 7.0

Experiment 1

Instruction: VPSRLW YMM1, YMM2, XMM0
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c5 ed d1 c8          	vpsrlw ymm1,ymm2,xmm0
   4:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   9:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  13:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  18:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 9.0
- Reference cycles: 7.75
- UOPS_EXECUTED.THREAD: 7.0

Experiment 2

Instruction: VPSRLW YMM1, YMM2, XMM0
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c5 ed d1 c8          	vpsrlw ymm1,ymm2,xmm0
   4:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   8:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   c:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  10:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  14:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 9.0
- Reference cycles: 8.0
- UOPS_EXECUTED.THREAD: 7.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPSRLW YMM1, YMM2, XMM0
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c5 ed d1 c8          	vpsrlw ymm1,ymm2,xmm0
   4:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   9:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  13:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  18:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS XMM0, XMM0, XMM0;
VPSRLW YMM2, YMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 9.0
- Reference cycles: 8.25
- UOPS_EXECUTED.THREAD: 7.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPSRLW YMM1, YMM2, XMM0
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c5 ed d1 c8          	vpsrlw ymm1,ymm2,xmm0
   4:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   8:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   c:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  10:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  14:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS XMM0, XMM0, XMM0;
VPSRLW YMM2, YMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 9.0
- Reference cycles: 7.75
- UOPS_EXECUTED.THREAD: 7.0

VPSRLW (YMM, YMM, XMM) - Latency

Operands

Latency operand 2 → 1: 1

Latency operand 3 → 1: 4

Latency operand 2 → 1: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 4

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)