VPSRLW (YMM, YMM, XMM) - Throughput and Uops (IACA 2.3)
With different registers for different operands
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 1.00 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.5 0.0 | 0.5 | 0.0 0.0 | 0.0 0.0 | 0.0 | 1.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
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| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm0, ymm1, xmm2
Total Num Of Uops: 2
With 11 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 11.00 Cycles Throughput Bottleneck: Backend. Port5
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 5.5 0.0 | 5.5 | 0.0 0.0 | 0.0 0.0 | 0.0 | 11.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm0, ymm1, xmm2
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm3, ymm1, xmm2
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm4, ymm1, xmm2
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm5, ymm1, xmm2
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm6, ymm1, xmm2
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm7, ymm1, xmm2
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm8, ymm1, xmm2
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm9, ymm1, xmm2
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm10, ymm1, xmm2
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm11, ymm1, xmm2
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm12, ymm1, xmm2
Total Num Of Uops: 22
With the same register for for different operands
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 3.81 Cycles Throughput Bottleneck: FrontEnd
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 0.5 0.0 | 0.5 | 0.0 0.0 | 0.0 0.0 | 0.0 | 1.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm0, ymm0, xmm0
Total Num Of Uops: 2
With 13 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 13.00 Cycles Throughput Bottleneck: Backend. Port5
Port Binding In Cycles Per Iteration:
---------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
---------------------------------------------------------------------------------------
| Cycles | 6.5 0.0 | 6.5 | 0.0 0.0 | 0.0 0.0 | 0.0 | 13.0 | 0.0 | 0.0 |
---------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 | |
---------------------------------------------------------------------------------
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm0, ymm0, xmm0
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm1, ymm1, xmm1
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm2, ymm2, xmm2
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm3, ymm3, xmm3
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm4, ymm4, xmm4
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm5, ymm5, xmm5
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm6, ymm6, xmm6
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm7, ymm7, xmm7
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm8, ymm8, xmm8
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm9, ymm9, xmm9
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm10, ymm10, xmm10
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm11, ymm11, xmm11
| 2 | 0.5 | 0.5 | | | | 1.0 | | | CP | vpsrlw ymm12, ymm12, xmm12
Total Num Of Uops: 26