VPSRLW (YMM, YMM, XMM) - Throughput and Uops (IACA 3.0)
With different registers for different operands
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 0.97 Cycles Throughput Bottleneck: Dependency chains
Loop Count: 32
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 1.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm0, ymm1, xmm2
Total Num Of Uops: 2
With 11 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 10.95 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 11.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 11.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm0, ymm1, xmm2
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm3, ymm1, xmm2
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm4, ymm1, xmm2
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm5, ymm1, xmm2
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm6, ymm1, xmm2
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm7, ymm1, xmm2
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm8, ymm1, xmm2
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm9, ymm1, xmm2
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm10, ymm1, xmm2
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm11, ymm1, xmm2
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm12, ymm1, xmm2
Total Num Of Uops: 22
With the same register for for different operands
With 1 independent instruction
Throughput Analysis Report
--------------------------
Block Throughput: 3.90 Cycles Throughput Bottleneck: Backend
Loop Count: 43
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 1.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 1.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm0, ymm0, xmm0
Total Num Of Uops: 2
With 13 independent instructions
Throughput Analysis Report
--------------------------
Block Throughput: 12.95 Cycles Throughput Bottleneck: Backend
Loop Count: 22
Port Binding In Cycles Per Iteration:
--------------------------------------------------------------------------------------------------
| Port | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
--------------------------------------------------------------------------------------------------
| Cycles | 13.0 0.0 | 0.0 | 0.0 0.0 | 0.0 0.0 | 0.0 | 13.0 | 0.0 | 0.0 |
--------------------------------------------------------------------------------------------------
| Num Of | Ports pressure in cycles | |
| Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | 6 | 7 |
-----------------------------------------------------------------------------------------
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm0, ymm0, xmm0
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm1, ymm1, xmm1
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm2, ymm2, xmm2
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm3, ymm3, xmm3
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm4, ymm4, xmm4
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm5, ymm5, xmm5
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm6, ymm6, xmm6
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm7, ymm7, xmm7
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm8, ymm8, xmm8
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm9, ymm9, xmm9
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm10, ymm10, xmm10
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm11, ymm11, xmm11
| 2 | 1.0 | | | | | 1.0 | | | vpsrlw ymm12, ymm12, xmm12
Total Num Of Uops: 26