BTS (M32, R32)

Operands

• Operand 1 (r/w): Memory
• Operand 2 (r): Register (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D)
• Operand 3 (w, suppressed): Flags (AF: undef, CF: w, OF: undef, PF: undef, SF: undef)

Available performance data

• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• Ivy Bridge
• Sandy Bridge
• Westmere
• Nehalem
• Wolfdale
• Conroe
• Tremont
• Goldmont Plus
• Goldmont
• Airmont
• Bonnell
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤12
  • Latency operand 1 → 1 (address, index register): ≤12
  • Latency operand 1 → 1 (memory): 7
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤6
  • Latency operand 2 → 1: ≤18
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 1.60
  • Measured (loop): 5.00
  • Measured (unrolled): 4.96
• Number of μops
  • Executed: 11
  • Retire slots: 10
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 3*p0156B+2*p06+1*p1+2*p15B+1*p23A+1*p49+1*p78

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤33
  • Latency operand 1 → 1 (address, index register): ≤33
  • Latency operand 1 → 1 (memory): 14
  • Latency operand 1 → 3 (address, base register): 11
  • Latency operand 1 → 3 (address, index register): 12
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 2 → 1: ≤35
  • Latency operand 2 → 3: 9
• Throughput
  • Measured (loop): 13.07
  • Measured (unrolled): 13.95
• Number of μops
  • Executed: 10
  • Microcode Sequencer (MS): 9
  • Requires the complex decoder

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 7
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 7
  • Latency operand 1 → 3 (memory): ≤6
  • Latency operand 2 → 1: ≤18
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 10
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+4*p0156+3*p06+1*p23+1*p49+1*p78

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 7
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 7
  • Latency operand 1 → 3 (memory): ≤6
  • Latency operand 2 → 1: ≤18
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 10
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+4*p0156+3*p06+1*p23+1*p49+1*p78

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 7
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 7
  • Latency operand 1 → 3 (memory): ≤6
  • Latency operand 2 → 1: ≤18
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 10
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+4*p0156+3*p06+1*p23+1*p49+1*p78

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 4
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤3
  • Latency operand 2 → 1: ≤17
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 10
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+3*p0156+3*p06+1*p1+2*p23+1*p4

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 4
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤3
  • Latency operand 2 → 1: ≤17
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 10
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+3*p0156+3*p06+1*p1+2*p23+1*p4

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 4
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤3
  • Latency operand 2 → 1: ≤17
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 10
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+3*p0156+3*p06+1*p1+2*p23+1*p4

Coffee Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 4
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤3
  • Latency operand 2 → 1: ≤17
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 10
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+3*p0156+3*p06+1*p1+2*p23+1*p4

Kaby Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 4
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤3
  • Latency operand 2 → 1: ≤17
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 10
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+3*p0156+3*p06+1*p1+2*p23+1*p4

Skylake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 4
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤3
  • Latency operand 2 → 1: ≤17
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 10
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+3*p0156+3*p06+1*p1+2*p23+1*p4

Broadwell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤16
  • Latency operand 1 → 1 (address, index register): ≤16
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤5
  • Latency operand 2 → 1: ≤14
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 10
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 1*p015+3*p0156+3*p06+1*p1+2*p23+1*p4

Haswell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤16
  • Latency operand 1 → 1 (address, index register): ≤16
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤5
  • Latency operand 2 → 1: ≤14
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.00
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 10
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 4*p0156+3*p06+1*p1+2*p23+1*p4
• IACA 2.1
• Latency: 5
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 3
• Port usage: 1*p23+1*p237+1*p4

Ivy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤5
  • Latency operand 2 → 1: ≤14
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.67
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 11
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 4*p015+2*p05+1*p1+2*p23+1*p4+1*p5
• IACA 2.1
• Latency: 9
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 6
• Port usage: 1*p015+1*p05+2*p23+1*p4+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 6
• Port usage: 1*p015+1*p05+2*p23+1*p4+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.10
• Number of μops: 6
• Port usage: 1*p015+1*p05+2*p23+1*p4+1*p5

Sandy Bridge

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤5
  • Latency operand 2 → 1: ≤14
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.67
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 11
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 6
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 4*p015+2*p05+1*p1+2*p23+1*p4+1*p5
• IACA 2.1
• Latency: 9
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 6
• Port usage: 1*p015+1*p05+2*p23+1*p4+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 6
• Port usage: 1*p015+1*p05+2*p23+1*p4+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.10
• Number of μops: 6
• Port usage: 1*p015+1*p05+2*p23+1*p4+1*p5

Westmere

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤5
  • Latency operand 2 → 1: ≤13
  • Latency operand 2 → 3: 9
• Throughput
  • Computed from the port usage: 2.67
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 11
  • Microcode Sequencer (MS): 18
  • Requires the complex decoder
• Port usage: 5*p015+2*p05+1*p1+1*p2+1*p3+1*p4
• IACA 2.1
• Latency: 8
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 6
• Port usage: 2*p015+1*p05+1*p2+1*p3+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 6
• Port usage: 2*p015+1*p05+1*p2+1*p3+1*p4

Nehalem

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤5
  • Latency operand 2 → 1: ≤13
  • Latency operand 2 → 3: 9
• Throughput
  • Computed from the port usage: 2.67
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
  • Retire slots: 11
  • Microcode Sequencer (MS): 18
  • Requires the complex decoder
• Port usage: 5*p015+2*p05+1*p1+1*p2+1*p3+1*p4
• IACA 2.1
• Latency: 8
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 6
• Port usage: 2*p015+1*p05+1*p2+1*p3+1*p4
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 6
• Port usage: 2*p015+1*p05+1*p2+1*p3+1*p4

Wolfdale

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤5
  • Latency operand 2 → 1: ≤14
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.67
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
• Port usage: 1*p0+5*p015+1*p05+1*p2+1*p3+1*p4+1*p5 (if an indexed addressing mode is used: 1*p0+5*p015+2*p05+1*p2+1*p3+1*p4)

Conroe

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤10
  • Latency operand 1 → 1 (address, index register): ≤10
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 6
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤5
  • Latency operand 2 → 1: ≤14
  • Latency operand 2 → 3: 10
• Throughput
  • Computed from the port usage: 2.67
  • Measured (loop): 5.00
  • Measured (unrolled): 5.00
• Number of μops
  • Executed: 11
• Port usage: 1*p0+5*p015+2*p05+1*p2+1*p3+1*p4

Tremont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤34
  • Latency operand 1 → 1 (address, index register): ≤34
  • Latency operand 1 → 1 (memory): 6
  • Latency operand 1 → 3 (address, base register): 11
  • Latency operand 1 → 3 (address, index register): 11
  • Latency operand 1 → 3 (memory): ≤7
  • Latency operand 2 → 1: ≤36
  • Latency operand 2 → 3: 8
• Throughput
  • Measured (loop): 13.00
  • Measured (unrolled): 13.00
• Number of μops
  • Executed: 11
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder

Goldmont Plus

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤33
  • Latency operand 1 → 1 (address, index register): ≤33
  • Latency operand 1 → 1 (memory): 7
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 7
  • Latency operand 1 → 3 (memory): ≤7
  • Latency operand 2 → 1: ≤35
  • Latency operand 2 → 3: 8
• Throughput
  • Measured (loop): 7.00
  • Measured (unrolled): 7.00
• Number of μops
  • Executed: 9
  • Microcode Sequencer (MS): 9
  • Requires the complex decoder

Goldmont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤12
  • Latency operand 1 → 1 (address, index register): ≤12
  • Latency operand 1 → 1 (memory): 7
  • Latency operand 1 → 3 (address, base register): 11
  • Latency operand 1 → 3 (address, index register): 11
  • Latency operand 1 → 3 (memory): ≤7
  • Latency operand 2 → 1: ≤14
  • Latency operand 2 → 3: 8
• Throughput
  • Measured (loop): 12.00
  • Measured (unrolled): 12.00
• Number of μops
  • Executed: 10
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder

Airmont

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤12
  • Latency operand 1 → 1 (address, index register): ≤12
  • Latency operand 1 → 1 (memory): 9
  • Latency operand 1 → 3 (address, base register): 9
  • Latency operand 1 → 3 (address, index register): 9
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 2 → 1: ≤13
  • Latency operand 2 → 3: 9
• Throughput
  • Measured (loop): 10.00
  • Measured (unrolled): 10.00
• Number of μops
  • Executed: 8
  • Microcode Sequencer (MS): 8
  • Requires the complex decoder

Bonnell

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤11
  • Latency operand 1 → 1 (address, index register): ≤11
  • Latency operand 1 → 1 (memory): 11
  • Latency operand 1 → 3 (address, base register): 11
  • Latency operand 1 → 3 (address, index register): 10
  • Latency operand 1 → 3 (memory): ≤10
  • Latency operand 2 → 1: ≤11
  • Latency operand 2 → 3: 10
• Throughput
  • Measured (loop): 11.05
  • Measured (unrolled): 11.00
• Number of μops
  • Executed: 10
  • Microcode Sequencer (MS): 10
  • Requires the complex decoder

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤45
  • Latency operand 1 → 1 (address, index register): ≤18
  • Latency operand 1 → 1 (memory): 8
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 2 → 1: ≤46
  • Latency operand 2 → 3: 8
• Throughput
  • Measured (loop): 3.00
  • Measured (unrolled): 3.00
• Number of μops
  • Executed: 9

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤44
  • Latency operand 1 → 1 (address, index register): ≤17
  • Latency operand 1 → 1 (memory): 8
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 6
  • Latency operand 1 → 3 (memory): ≤7
  • Latency operand 2 → 1: ≤45
  • Latency operand 2 → 3: 8
• Throughput
  • Measured (loop): 3.00
  • Measured (unrolled): 3.00
• Number of μops
  • Executed: 9

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤17
  • Latency operand 1 → 1 (address, index register): ≤17
  • Latency operand 1 → 1 (memory): 9
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 7
  • Latency operand 1 → 3 (memory): ≤8
  • Latency operand 2 → 1: ≤46
  • Latency operand 2 → 3: 8
• Throughput
  • Measured (loop): 3.00
  • Measured (unrolled): 3.00
• Number of μops
  • Executed: 8

AMD Zen+

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤21
  • Latency operand 1 → 1 (address, index register): ≤21
  • Latency operand 1 → 1 (memory): 9
  • Latency operand 1 → 3 (address, base register): 7
  • Latency operand 1 → 3 (address, index register): 7
  • Latency operand 1 → 3 (memory): ≤7
  • Latency operand 2 → 1: ≤46
  • Latency operand 2 → 3: 8
• Throughput
  • Measured (loop): 3.00
  • Measured (unrolled): 3.00
• Number of μops
  • Executed: 8