BTS (M32, R32) - Latency


Operands


Latency operand 1 → 1 (address, base register): ≤16

Latency operand 1 → 1 (address, index register): ≤16

Latency operand 1 → 1 (memory): 6

Latency operand 1 → 3 (address, base register): 9

Latency operand 1 → 3 (address, index register): 9

Latency operand 1 → 3 (memory): ≤5

Latency operand 2 → 1: ≤14

Latency operand 2 → 3: 10


Latency operand 1 → 1 (address, base register): ≤16

Experiment 1 (with R8D=0)

Experiment 2 (with R8D=1)

Experiment 3 (with R8D=2)

Experiment 4 (with additional nop, with R8D=0)

Experiment 5 (with additional nop, with R8D=1)

Experiment 6 (with additional nop, with R8D=2)


Latency operand 1 → 1 (address, index register): ≤16

Experiment 1

Experiment 2 (with additional nop)


Latency operand 1 → 1 (memory): 6

Experiment 1 (with R8D=0)

Experiment 2 (with R8D=1)

Experiment 3 (with R8D=2)

Experiment 4 (with R8D=0)

Experiment 5 (with R8D=1)

Experiment 6 (with R8D=2)


Latency operand 1 → 3 (address, base register): 9

Experiment 1 (with R8D=0)

Experiment 2 (with R8D=0, with dependency-breaking instructions)

Experiment 3 (with R8D=1)

Experiment 4 (with R8D=1, with dependency-breaking instructions)

Experiment 5 (with R8D=2)

Experiment 6 (with R8D=2, with dependency-breaking instructions)


Latency operand 1 → 3 (address, index register): 9

Experiment 1

Experiment 2 (with dependency-breaking instructions)


Latency operand 1 → 3 (memory): ≤5

Experiment 1 (with R8D=0)

Experiment 2 (with R8D=1)

Experiment 3 (with R8D=2)


Latency operand 2 → 1: ≤14

Experiment 1


Latency operand 2 → 3: 10

Experiment 1