VPGATHERDD (YMM, VSIB_YMM, YMM)

Summary:	"Gather Packed Dword Values Using Signed Dword/Qword Indices"
Reference:	https://www.felixcloutier.com/x86/VPGATHERDD:VPGATHERQD.html
Extension:	AVX2GATHER
Category:	AVX2GATHER
ISA-Set:	AVX2GATHER
CPL:	3
iform:	VPGATHERDD_YMMu32_MEMd_YMMi32_VL256
iclass:	VPGATHERDD
ASM:	VPGATHERDD

Operands

Operand 1 (r/w): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)
Operand 2 (r): Memory
Operand 3 (r/w): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)

Available performance data

Alder Lake-P
Alder Lake-E
Rocket Lake
Tiger Lake
Ice Lake
Cascade Lake
Cannon Lake
Skylake-X
Coffee Lake
Kaby Lake
Skylake
Broadwell
Haswell
AMD Zen 4
AMD Zen 3
AMD Zen 2
AMD Zen+

Alder Lake-P

Measurements

Latencies
Throughput
- Computed from the port usage: 2.67
- Measured (loop): 3.03
- Measured (unrolled): 3.03
Number of μops
- Executed: 7
- Retire slots: 5
- Decoded (MITE): 5
- Microcode Sequencer (MS): 0
- Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p015+2*p15+8*p23A

Alder Lake-E

Measurements

Latencies
- Latency operand 1 → 1: 30
- Latency operand 1 → 3: 17
- Latency operand 2 → 1 (address, base register): ≤21
- Latency operand 2 → 1 (address, index register): ≤33
- Latency operand 2 → 1 (memory): ≤19
- Latency operand 2 → 3 (address, base register): ≤8
- Latency operand 2 → 3 (address, index register): ≤19
- Latency operand 2 → 3 (memory): ≤6
- Latency operand 3 → 1: 32
- Latency operand 3 → 3: 18
Throughput
- Measured (loop): 30.17
- Measured (unrolled): 31.82
Number of μops
- Executed: 68
- Microcode Sequencer (MS): 67
- Requires the complex decoder

Rocket Lake

Measurements

Latencies
Throughput
- Computed from the port usage: 4.00
- Measured (loop): 5.00
- Measured (unrolled): 5.00
Number of μops
- Executed: 5
- Retire slots: 4
- Decoded (MITE): 4
- Microcode Sequencer (MS): 0
- Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p015+1*p15+8*p23

Tiger Lake

Measurements

Latencies
Throughput
- Computed from the port usage: 4.00
- Measured (loop): 5.00
- Measured (unrolled): 5.00
Number of μops
- Executed: 5
- Retire slots: 4
- Decoded (MITE): 4
- Microcode Sequencer (MS): 0
- Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p015+1*p15+8*p23

Ice Lake

Measurements

Latencies
Throughput
- Computed from the port usage: 4.00
- Measured (loop): 5.00
- Measured (unrolled): 5.00
Number of μops
- Executed: 5
- Retire slots: 4
- Decoded (MITE): 4
- Microcode Sequencer (MS): 0
- Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p015+1*p15+8*p23

Cascade Lake

Measurements

Latencies
Throughput
- Computed from the port usage: 4.00
- Measured (loop): 5.00
- Measured (unrolled): 5.00
Number of μops
- Executed: 5
- Retire slots: 4
- Decoded (MITE): 4
- Microcode Sequencer (MS): 0
- Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p015+8*p23+1*p5

Cannon Lake

Measurements

Latencies
Throughput
- Computed from the port usage: 4.00
- Measured (loop): 5.00
- Measured (unrolled): 5.00
Number of μops
- Executed: 5
- Retire slots: 4
- Decoded (MITE): 4
- Microcode Sequencer (MS): 0
- Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p015+8*p23+1*p5

Skylake-X

Measurements

Latencies
Throughput
- Computed from the port usage: 4.00
- Measured (loop): 5.00
- Measured (unrolled): 5.00
Number of μops
- Executed: 5
- Retire slots: 4
- Decoded (MITE): 4
- Microcode Sequencer (MS): 0
- Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p015+8*p23+1*p5

IACA 2.3

Throughput
- Computed from the port usage: 4.00
- IACA: 5.29
Number of μops: 5
Port usage: 1*p0+1*p015+8*p23+1*p5

IACA 3.0

Throughput
- Computed from the port usage: 4.00
- IACA: 3.99
Number of μops: 5
Port usage: 1*p0+1*p015+8*p23+1*p5

Coffee Lake

Measurements

Latencies
Throughput
- Computed from the port usage: 4.00
- Measured (loop): 5.00
- Measured (unrolled): 5.00
Number of μops
- Executed: 5
- Retire slots: 4
- Decoded (MITE): 4
- Microcode Sequencer (MS): 0
- Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p015+8*p23+1*p5

Kaby Lake

Measurements

Latencies
Throughput
- Computed from the port usage: 4.00
- Measured (loop): 5.00
- Measured (unrolled): 5.00
Number of μops
- Executed: 5
- Retire slots: 4
- Decoded (MITE): 4
- Microcode Sequencer (MS): 0
- Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p015+8*p23+1*p5

Skylake

Measurements

Latencies
Throughput
- Computed from the port usage: 4.00
- Measured (loop): 5.00
- Measured (unrolled): 5.00
Number of μops
- Executed: 5
- Retire slots: 4
- Decoded (MITE): 4
- Microcode Sequencer (MS): 0
- Requires the complex decoder (1 other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+1*p015+8*p23+1*p5

IACA 2.3

Throughput
- Computed from the port usage: 4.00
- IACA: 5.29
Number of μops: 5
Port usage: 1*p0+1*p015+8*p23+1*p5

IACA 3.0

Throughput
- Computed from the port usage: 4.00
- IACA: 3.99
Number of μops: 5
Port usage: 1*p0+1*p015+8*p23+1*p5

Broadwell

Measurements

Latencies
Throughput
- Computed from the port usage: 4.00
- Measured (loop): 6.00
- Measured (unrolled): 6.00
Number of μops
- Executed: 13
- Retire slots: 14
- Decoded (MITE): 4
- Microcode Sequencer (MS): 10
- Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p015+8*p23+1*p4+3*p5

IACA 2.2

Throughput
- Computed from the port usage: 4.00
- IACA: 7.00 (with the -no_interiteration flag: 11.52)
Number of μops: 13
Port usage: 1*p0156+8*p23+4*p5

IACA 2.3

Throughput
- Computed from the port usage: 4.00
- IACA: 7.00
Number of μops: 13
Port usage: 1*p0156+8*p23+4*p5

IACA 3.0

Throughput
- Computed from the port usage: 4.00
- IACA: 6.99
Number of μops: 14
Port usage: 1*p0156+8*p23+1*p4+4*p5

Haswell

Measurements

Latencies
Throughput
- Computed from the port usage: 7.00
- Measured (loop): 11.00
- Measured (unrolled): 11.00
Number of μops
- Executed: 34
- Retire slots: 34
- Decoded (MITE): 3
- Microcode Sequencer (MS): 31
- Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
Port usage: 5*p0+7*p015+9*p06+1*p15+8*p23+4*p5

IACA 2.1

Latency: 19
Throughput
- Computed from the port usage: 4.00
- IACA: 13.50 (with the -no_interiteration flag: 13.50)
Number of μops: 5
Port usage: 1*p0+1*p0156+8*p23+1*p5

IACA 2.2

Throughput
- Computed from the port usage: 6.50
- IACA: 10.00 (with the -no_interiteration flag: 10.00)
Number of μops: 34
Port usage: 5*p0+9*p015+8*p06+1*p15+8*p23+3*p5

IACA 2.3

Throughput
- Computed from the port usage: 6.50
- IACA: 10.01
Number of μops: 34
Port usage: 5*p0+9*p015+8*p06+1*p15+8*p23+3*p5

IACA 3.0

Throughput
- Computed from the port usage: 6.50
- IACA: 10.29
Number of μops: 34
Port usage: 5*p0+9*p015+8*p06+1*p15+8*p23+3*p5

AMD Zen 4

Measurements

Latencies
Throughput
- Computed from the port usage: 4.50
- Measured (loop): 8.00
- Measured (unrolled): 8.00
Number of μops
- Executed: 42
Port usage: 8*FP01+1*FP12+6*FP123+2*FP23+9*FP45

AMD Zen 3

Measurements

Latencies
Throughput
- Computed from the port usage: 7.00
- Measured (loop): 8.00
- Measured (unrolled): 8.00
Number of μops
- Executed: 39
Port usage: 1*FP01+7*FP0123+7*FP1+9*FP45

AMD Zen 2

Measurements

Latencies
Throughput
- Measured (loop): 16.00
- Measured (unrolled): 16.00
Number of μops
- Executed: 60

AMD Zen+

Measurements

Latencies
Throughput
- Measured (loop): 20.00
- Measured (unrolled): 20.00
Number of μops
- Executed: 65