VPGATHERDD (YMM, VSIB_YMM, YMM) - Latency


Operands


Latency operand 1 → 1: 30

Latency operand 1 → 3: 17

Latency operand 2 → 1 (address, base register): ≤21

Latency operand 2 → 1 (address, index register): ≤33

Latency operand 2 → 1 (memory): ≤19

Latency operand 2 → 3 (address, base register): ≤8

Latency operand 2 → 3 (address, index register): ≤19

Latency operand 2 → 3 (memory): ≤6

Latency operand 3 → 1: 32

Latency operand 3 → 3: 18


Latency operand 1 → 1: 30

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)


Latency operand 1 → 3: 17

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 1 (address, base register): ≤21

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 1 (address, index register): ≤33

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 1 (memory): ≤19

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 3 (address, base register): ≤8

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 3 (address, index register): ≤19

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)


Latency operand 2 → 3 (memory): ≤6

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 1: 32

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)


Latency operand 3 → 3: 18

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)